DEADLOCK RECOVERY TECHNIQUE IN BUS ENHANCED NOC ARCHITECTURE

DEADLOCK RECOVERY TECHNIQUE IN BUS ENHANCED NOC ARCHITECTURE

Saeid Sharifian Nia1, Abbas Vafaei2, Hamid Shahimohamadi3

1Department of Computer Engineering, University of Isfahan, Isfahan, Iran

2Department of Computer Engineering, University of Isfahan, Isfahan, Iran

3Department of Computer Engineering, Shahid Beheshti University, Tehran, Iran

ABSTRACT

Increase in the speed of processors has led to crucial role of communication in the performance of systems. As a result, routing is taken into consideration as one of the most important subjects of the Network on Chip architecture. Routing algorithms to deadlock avoidance prevent packets route completely based on network traffic condition by means of restricting the route of packets. This action leads to less performance especially in non-uniform traffic patterns. On the other hand True Fully Adoptive Routing algorithm provides routing of packets completely based on traffic condition. However, deadlock detection and recovery mechanisms are needed to handle deadlocks. Use of global bus beside NoC as a parallel supportive environment, provide platform to offer advantages of both features of bus and NoC. This bus is useful for broadcast and multicast operations, sending delay sensitive signals, system management and other services. In this research, we use this bus as an escaping path for deadlock recovery technique. According to simulation results, this bus is suitable platform for deadlock recovery technique. 

KEYWORDS

Network on chip, deadlock recovery, deadlock detection, routing algorithm, bus enhanced NoC. 

Original Source Link : http://aircconline.com/vlsics/V3N4/3412vlsics01.pdf

http://airccse.org/journal/vlsi/vol3.html

EFFICIENT IMPLEMENTATION OF 16-BIT MULTIPLIER-ACCUMULATOR USING RADIX-2 MODIFIED BOOTH ALGORITHM AND SPST ADDER USING VERILOG

EFFICIENT IMPLEMENTATION OF 16-BIT MULTIPLIER-ACCUMULATOR USING RADIX-2 MODIFIED BOOTH ALGORITHM AND SPST ADDER USING VERILOG

Addanki Purna Ramesh1, Dr.A.V. N. Tilak2 and Dr.A.M.Prasad3

1Department of ECE, Sri Vasavi Engineering College, Pedatadepalli, Tadepalligudem, India

2Department of ECE, Gudlavalleru Engineering College, Gudlavalleru, India

3Department of ECE, UCEK, JNTU, Kakinada, India

ABSTRACT

In this paper, we propose a new multiplier-and-accumulator (MAC) architecture for low power and high speed arithmetic. High speed and low power MAC units are required for applications of digital signal processing like Fast Fourier Transform, Finite Impulse Response filters, convolution etc. For improving the speed and reducing the dynamic power, there is a need to reduce the glitches (1 to 0 transition) and spikes (0 to 1 transition). Adder designed using spurious power suppression technique (SPST) avoids the unwanted glitches and spikes, thus minimizing the switching power dissipation and hence the dynamic power. Radix -2 modified booth algorithm reduces the number of partial products to half by grouping of bits from the multiplier term, which improves the speed. The proposed radix-2 modified Booth algorithm

MAC with SPST gives a factor of 5 less delay and 7% less power consumption as compared to array MAC

KEYWORDS

Radix -2 modified booth algorithm, Digital signal processing, spurious power suppression Technique, Verilog.

Original Source Link : http://aircconline.com/vlsics/V3N3/3312vlsics10.pdf

http://airccse.org/journal/vlsi/vol3.html

DESIGN AND PERFORMANCE ANALYSIS OF ULTRA LOW POWER 6T SRAM USING ADIABATIC TECHNIQUE

DESIGN AND PERFORMANCE ANALYSIS OF ULTRA LOW POWER 6T SRAM USING ADIABATIC TECHNIQUE

Mr. Sunil Jadav1, Mr. Vikrant2, Dr. Munish Vashisath3

2PG Student, Electrical & Electronics Engineering Dept. YMCAUS&T, Faridabad,Haryana

1,3Faculty, Electrical & Electronics Engineering Dept. YMCAUS&T, Faridabad, Haryana

ABSTRACT: 

Power consumption has become a critical concern in both high performance and portable applications. Methods for power reduction based on the application of adiabatic techniques to CMOS circuits have recently come under renewed investigation. In thermodynamics, an adiabatic energy transfer through a dissipative medium is one in which losses are made arbitrarily small by causing the transfer to occur sufficiently slowly. In this work adiabatic technique is used for reduction of average power

dissipation. Simulation of 6T SRAM cell has been done for 180nm CMOS technology. It shows that average power dissipation is reduced up to 75% using adiabatic technique and also shows the effect on static noise margin.

Keywords

Adiabatic Logic, Average Power dissipation, Static Noise Margin

Original source Link : http://aircconline.com/vlsics/V3N3/3312vlsics09.pdf

http://airccse.org/journal/vlsi/vol3.html

Design of Efficient Adder Circuits Using PROPOSED PARITY PRESERVING GATE (PPPG)

Design of Efficient Adder Circuits Using PROPOSED PARITY PRESERVING GATE (PPPG)

Krishna Murthy M, Gayatri G, Manoj Kumar R

Department of ECE, MVGRCE, Vizianagaram, Andhra Pradesh 

ABSTRACT

Reversible logic is becoming an important research area which aims mainly to reduce power dissipation during computing. In this paper we introduce a new parity preserving reversible gate PPPG (a 5x5 gate). This gate is universal in the sense it can synthesize any arbitrary Boolean function. It is also a parity preserving gate in which the parity of input matches the parity of the output. This parity preserving gate allows any single fault to be detected at the circuit’s primary outputs. By using one PPPG a fault tolerant reversible full adder circuit can be realized. The proposed fault tolerant full adder (PFTFA) is used to design other arithmetic logic circuits for which it is used as the fundamental building block. The PFTFA gate is also used to implement high speed adders which are efficient basic building blocks of logic circuits. It has also been demonstrated that the proposed high speed adders are efficient in terms of gate count, garbage outputs and constant inputs than the existing counterparts.

KEYWORDS

Reversible logic, Garbage output, Reversible gate, Proposed Parity Preserving Gate, Constant inputs and Proposed fault tolerant full adder, Carry Skip Adder, Carry Look Ahead Adder, Ripple carry Adder 

Original Source Link : http://aircconline.com/vlsics/V3N3/3312vlsics08.pdf

http://airccse.org/journal/vlsi/vol3.html

PERFORMANCE EVALUATION OF CDMAROUTER FOR NETWORK - ON - CHIP

PERFORMANCE EVALUATION OF CDMAROUTER FOR NETWORK - ON - CHIP

Anant W. Hinganikar1, Mahendra A. Gaikwad2 and Rajendra M. Patrikar3

1Department of E&T, B.D.College of Engineering, Sevagram (Wardha)-India

2Department of EC, B.D.College of Engineering, Sevagram (Wardha)-India

3Department of EC, VNIT), Nagpur-India

Abstract

This paper presents the performance evaluation of router based on code division multiple access technique (CDMA) for Network-on-Chip (NoC). The design is synthesized using Xilinx Virtex4 XC4VLX200 device. The functional behavior is verified using Modelsim XE III 6.2 C. The delay and throughput values are obtained for variable payload sizes. Throughput-Power and Delay-Power characteristics are also verified for NoC.

Keywords

CDMA, Walsh Code, Router, NoC 

Original Source Link : http://aircconline.com/vlsics/V3N3/3312vlsics07.pdf

http://airccse.org/journal/vlsi/vol3.html

DESIGN AND PERFORMANCE ANALYSIS OF NINE STAGES CMOS BASED RING OSCILLATOR

DESIGN AND PERFORMANCE ANALYSIS OF NINE STAGES CMOS BASED RING OSCILLATOR

Sushil Kumar and Gurjit Kaur

School of Information and Communication Technology Gautam Buddha University, UP, India

ABSTRACT

This paper deals with the design and performance analysis of a ring oscillator using CMOS 45nm technology process in Cadence virtuoso environment. The design of optimal Analog and Mixed Signal (AMS) very large scale integrated circuits (VLSI) is a challenging task for the integrated circuit(IC) designer. A Ring Oscillator is an active device which is made up of odd number of NOT gates and whose output oscillates between two voltage levels representing high and low. There are a number of challenges ahead while designing the CMOS Ring Oscillator which are delay, noise and glitches. CMOS is the technology of choice for many applications, CMOS oscillators with low power, phase noise and timing jitter are highly desired. In this paper, we have designed a CMOS ring oscillator with nine stages.Previously, the researchers were unable to reduce the phase noise in ring oscillators substantially with nine stages. We have successfully reduced the phase noise to -6.4kdBc/Hz at 2GHz center frequency of oscillation.

KEYWORDS

Analog and mixed signal (AMS), VLSI circuit, CMOS Ring oscillator (RO), integrated circuit (IC), phase noise, center frequency of oscillation 

Original Source Link : http://aircconline.com/vlsics/V3N3/3312vlsics06.pdf

http://airccse.org/journal/vlsi/vol3.html

A HIGH EFFICIENCY CHARGE PUMP FOR LOW VOLTAGE DEVICES

A HIGH EFFICIENCY CHARGE PUMP FOR LOW VOLTAGE DEVICES

Aamna Anil1 and Ravi Kumar Sharma2

1Department of Electronics and Communication Engineering, Lovely Professional University, Jalandhar, Punjab, India

2Department of Electronics and Communication Engineering, Lovely Professional University, Jalandhar, Punjab, India

ABSTRACT

A charge pump is a kind of DC to DC converter that uses capacitor as energy storage elements to create a higher or lower voltage power source. Charge pumps make use of switching devices for controlling the connection of voltage to the capacitor. Charge pumps have been used in the nonvolatile memories, such as EEPROM and Flash memories, for the programming of the floating-gate devices. They can also be used in the low-supply-voltage switched-capacitor systems that require high voltage to drive the analog switched. This paper includes voltage analysis of different charge pumps. On the basis of voltage analysis a new charge pump is proposed. 

Original Source Link : http://aircconline.com/vlsics/V3N3/3312vlsics05.pdf

http://airccse.org/journal/vlsi/vol3.html

A NOVEL FULL ADDER CELL BASED ON CARBON NANOTUBE FIELD EFFECT TRANSISTORS

A NOVEL FULL ADDER CELL BASED ON CARBON NANOTUBE FIELD EFFECT TRANSISTORS

Ali Ghorbani1 and Mehdi Sarkhosh1 and Elnaz Fayyazi 1 and Neda Mahmoudi 1 and Peiman Keshavarzian2

1Department of Computer Engineering, Science And Research Branch ,Islamic Azad University,Kerman,Iran

2Department of Computer Engineering, Kerman Branch ,Islamic Azad University,Kerman,Iran

ABSTRACT

Presenting a novel full adder cell will be increases all the arithmetic logic unit performance. In this paper, We present two new full adder cell designs using carbon nanotube field effect transistors (CNTFETs). In the first design we have 42 transistors and 5 pull-up resistance so that we have achieved an improvement in the output parameters. Simulations were carried out using HSPICE based on the CNTFET model with 0.9V VDD. The denouments results in that we have a considerable improvement in power, Delay and power delay product than the previous works.

KEYWORDS

Full Adder, Carbon Nano-tube, Carbon Nano-tube field effect transistor, Low power full adder, CNTFET

Original Source Link : http://aircconline.com/vlsics/V3N3/3312vlsics04.pdf

http://airccse.org/journal/vlsi/vol3.html

DESIGN AND PERFORMANCE ANALYSIS OF HYBRID ADDERS FOR HIGH SPEED ARITHMETIC CIRCUIT

DESIGN AND PERFORMANCE ANALYSIS OF HYBRID ADDERS FOR HIGH SPEED ARITHMETIC CIRCUIT

Rajkumar Sarma1 and Veerati Raju2

1School of Electronics Engineering, Lovely Professional University, Punjab (India)

2Department of VLSI, Lovely Professional University, Punjab (India)

ABSTRACT

Adder cells using Gate Diffusion Technique (GDI) & PTL-GDI technique are described in this paper. GDI technique allows reducing power consumption, propagation delay and low PDP (power delay product) whereas Pass Transistor Logic (PTL) reduces the count of transistors used to make different logic gates, by eliminating redundant transistors. Performance comparison with various Hybrid Adder is been presented. In this paper, we propose two new designs based on GDI & PTL techniques, which is found to be much more power efficient in comparison with existing design technique. Only 10 transistors are used to implement the SUM & CARRY function for both the designs. The SUM and CARRY cell are implemented in a cascaded way i.e. firstly the XOR cell is implemented and then using XOR as input SUM as well as CARRY cell is implemented. For Proposed GDI adder the SUM as well as CARRY cell is designed using GDI technique. On the other hand in Proposed PTL-GDI adder the SUM cell is constructed using PTL technique and the CARRY cell is designed using GDI technique. The advantages of both the designs are discussed. The significance of these designs is substantiated by the simulation results obtained from Cadence Virtuoso 180nm environment.

KEYWORDS

GDI, PTL, PDP, low power, Full Adder & VLSI.

Original Source Link : http://aircconline.com/vlsics/V3N3/3312vlsics03.pdf

http://airccse.org/journal/vlsi/vol3.html

CNFET BASED BASIC GATES AND A NOVEL FULLADDER CELL

CNFET BASED BASIC GATES AND A NOVEL FULLADDER CELL

Fazel Sharifi1, Amir Momeni1 and keivan Navi1

Department of Electrical and Computer Engineering, Shahid Beheshti University,Tehran, Iran

ABSTRACT

In this paper two novel high performance designs for AND and OR basic gates and a novel Full-Adder Cell are presented. These designs are based on carbon nanotube technology. In order to compare the proposed designs with previous ones both MOSFET based and CNFET based circuits are selected. By the way the proposed designs have better performance in comparison with previous designs in terms of speed, power consumption and power-delay product (PDP).

KEYWORDS

CNFET, MOSFET, Full-Adder cell, Basic gates.

Original Source Link : http://aircconline.com/vlsics/V3N3/3312vlsics02.pdf

http://airccse.org/journal/vlsi/vol3.html

October - International journal of VLSI design & Communication Systems (...

A COMPARATIVE STUDY OF ULTRA-LOW VOLTAGE DIGITAL CIRCUIT DESIGN

A COMPARATIVE STUDY OF ULTRA-LOW VOLTAGE DIGITAL CIRCUIT DESIGN

Aaron Arthurs, Justin Roark, and Jia Di

Computer Engineering and Computer Science Department, University of Arkansas Fayetteville, Arkansas, USA

ABSTRACT

Ultra-low voltage digital circuit design is an active research area, especially for portable applications such as wearable electronics, intelligent remote sensors, implantable medical devices, and energy-harvesting systems. Due to their application scenarios and circuit components, two major goals for these systems are minimizing energy consumption and improving compatibility with low-voltage power supplies and analog components. The most effective solution to achieve these goals is to reduce the supply voltage, which, however, raises the issue of operability. At ultra-low supply voltages, the integrity of digital signals degrades dramatically due to the indifference between active and leakage currents. In addition, the system timing becomes more unpredictable as the impact of process and supply voltage variations being more significant at lower voltages. This paper presents a comparative study among three techniques for designing digital circuits operating at ultra-low voltages, i.e., Schmitt-triggered gate structure, delayinsensitive asynchronous logic, and Fully-Depleted Silicon-on-Insulator technology. Results show that despite the tradeoffs, all eight combinations of these techniques are viable for designing ultra-low voltage circuits. For a given application, the optimum circuit design can be selected from these combinations based on the lowest voltage, the dynamic range, the power budget, the performance requirement, and the available semiconductor process node.

KEYWORDS

Ultra-Low Voltage, Asynchronous Logic, Delay-Insensitive, Schmitt-Triggered, Silicon-on-Insulator

Original Source Link : http://aircconline.com/vlsics/V3N3/3312vlsics01.pdf

http://airccse.org/journal/vlsi/vol3.html

UVM BASED REUSABLE VERIFICATION IP FOR WISHBONE COMPLIANT SPI MASTER CORE

UVM BASED REUSABLE VERIFICATION IP FOR WISHBONE COMPLIANT SPI MASTER CORE

Lakhan Shiva Kamireddy1 and Lakhan Saiteja K2

1Department of Electrical and Computer Engineering,University of Colorado, Boulder, USA

2Indian Institute of Technology Kharagpur, West Bengal, India

ABSTRACT

The System on Chip design industry relies heavily on functional verification to ensure that the designs are bug-free. As design engineers are coming up with increasingly dense chips with much functionality, the functional verification field has advanced to provide modern verification techniques. In this paper, we present verification of a wishbone compliant Serial Peripheral Interface (SPI) Master core using a System Verilog based standard verification methodology, the Universal Verification Methodology (UVM). The reason for using UVM factory pattern with parameterized classes is to develop a robust and reusable verification IP. SPI is a full duplex communication protocol used to interface components most likely in embedded systems. We have verified an SPI Master IP core design that is wishbone compliant and compatible with SPI protocol and bus and furnished the results of our verification. We have used QuestaSim for simulation and analysis of waveforms, Integrated Metrics Center, Cadence for coverage analysis. We also propose interesting future directions for this work in developing reliable systems.

KEYWORDS

Functional Verification, QuestaSim, Reusable VIP, Simulation, SPI Master Core, Universal Verification Methodology (UVM) 

Original Source Link : http://aircconline.com/vlsics/V9N5/9518vlsi02.pdf

http://airccse.org/journal/vlsi/current.html

STATIC NOISE MARGIN OPTIMIZED 11NM SHORTED-GATE AND INDEPENDENT-GATE LOW POWER 6T FINFET SRAM TOPOLOGIES

STATIC NOISE MARGIN OPTIMIZED 11NM SHORTED-GATE AND INDEPENDENT-GATE LOW POWER 6T FINFET SRAM TOPOLOGIES

DustenVernor, Santosh Koppa and Eugene John

Department of Electrical andComputer Engineering, University of Texas at San Antonio, Texas, USA

ABSTRACT

This paper investigates the leakage current, static noise margin (SNM), delay and energy consumption of a 6 transistor FinFET based static random-access memory (SRAM) cell due to the variation in design and operating parameters of the SRAM cell. The SRAM design and operating parameters considered in this investigation are transistor sizing, supply voltage, word-line voltage, temperature and PFET and NFET back gate biasing. This investigation is performed using a 11nm FinFET shorted gate and low power technology models. Based on the investigation results, we propose a robust 6 transistor SRAM cells with optimized performance using shorted gate and independent gate low power FinFET models. By optimizing the design parameters of the cell, the shorted-gate design shows an improvement of read SNM of 261.56mV and an improvement of hold SNM of 87.68mV when compared to a shorted-gate cell with standard design parameters. The low-power design shows an improvement of read SNM of 146.18mV and a marginal decrease in hold SNM of 22.84mV when compared to a low-power cell with standard design parameters. Both the cells with the new optimized design parameters are shown to improve the overall SNM of the cells with minimal impact on the subthreshold leakage currents, performance and energy consumption.

KEYWORDS

SRAM, Leakage Power, Write Delay, Read Delay, FinFET, Static Noise Margin, SNM, Back GateBiasing.

Original Source Link : http://aircconline.com/vlsics/V9N5/9518vlsi01.pdf

http://airccse.org/journal/vlsi/current.html

Comparative Performance Analysis of XORXNOR Function Based High-Speed CMOS Full Adder Circuits For Low Voltage VLSI Design

Comparative Performance Analysis of XORXNOR Function Based High-Speed CMOS Full Adder Circuits For Low Voltage VLSI Design

Subodh Wairya1, Rajendra Kumar Nagaria2 and Sudarshan Tiwari2

1Department of Electronics Engineering, Institute of Engineering & Technology (I.E.T),Lucknow, India, 226021

2Department of ECED, Motilal Nehru National Institute of Technology (MNNIT), Allahabad, India, 211004

ABSTRACT

This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T)” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as it lowers power consumption by using XOR (3T) logic circuits. Gate Diffusion Input (GDI) technique of low-power digital combinatorial circuit design is also described. This technique helps in reducing the power consumption and the area of digital circuits while maintaining low complexity of logic design. This paper analyses, evaluates and compares the performance of various adder circuits. Several simulations conducted using different voltage supplies, load capacitors and temperature variation demonstrate the superiority of the XOR (3T) based full adder designs in term of delay, power and power delay product (PDP) compared to the other full adder circuits. Simulation results illustrate the superiority of the designed adder circuits against the conventional CMOS, TG and Hybrid full adder circuits in terms of power, delay and power delay product (PDP). 

KEYWORDS

Hybrid full adder, XOR-XNOR circuit, High Speed, Low Power, Very Large Scale Integrated (VLSI)Circuits,  

Original Scource Link : http://aircconline.com/vlsics/V3N2/3212vlsics19.pdf

http://airccse.org/journal/vlsi/vol3.html

Current Issue

Current Issue

October 2018, Volume 9, Number 5

Static Noise Margin Optimized 11nm Shorted-Gate and Independent-Gate Low Power 6T FINFET SRAM Topologies

DustenVernor, Santosh Koppa and Eugene John, University of Texas at San Antonio, USA

http://aircconline.com/vlsics/V9N5/9518vlsi01.pdf

UVM Based Reusable Verification IP for Wishbone Compliant SPI Master Core

Lakhan Shiva Kamireddy1 and Lakhan Saiteja K2, 1University of Colorado, USA and 2Indian Institute of Technology - Kharagpur, India

http://aircconline.com/vlsics/V9N5/9518vlsi02.pdf

VHDL Design for Image Segmentation using Gabor filter for Disease Detection

International Journal of VLSI design & Communication Systems (VLSICS)

Rucha R. Thakur1, Swati R. Dixit2 and Dr.A.Y.Deshmukh3

1Department of Electronics & Telecommunication Engineering, PG Student,G.H.Raisoni College of Engineering, Nagpur, India

2Department of Electronics & Telecommunication Engineering, Research Scholar,G.H.Raisoni College of Engineering, Nagpur, India

3Department of Electronics Engineering, Professor, G.H.Raisoni College of Engineering, Nagpur, India

Abstract

Tonsillitis, Tumor and many more skin diseases can be detected in its early-state and can be cured. For this a new idea for efficient Gabor filter design with improved data transfer rate, efficient noise reduction, less power consumption and reduced memory usage is proposed in this paper. The filter design is suitable for detecting the early stages of disease using textural properties of anatomical structures. The code for Gabor filter will be developed in VHDL using Modelsim and then implemented on SPARTAN-3E FPGA kit. These systems must provide both highly accurate and extremely fast processing of large amounts of image data.

Keywords

Segmentation, Medical image, Gabor algorithm, CORDIC algorithm, FPGA

Original Source Link : http://aircconline.com/vlsics/V3N2/3212vlsics18.pdf

http://airccse.org/journal/vlsi/vol3.html

Power consumption reduction in a SDR based wireless communication system using partial reconfigurable FPGA

Power consumption reduction in a SDR based wireless communication system using partial reconfigurable FPGA

1 Neenu Joseph, 2 Dr. P Nirmal Kumar

1Research Scholar, Department of ECE Anna University, Chennai,

2Associate Professor, Department of ECE, Anna University, Chennai,

ABSTRACT

The increase in the consumer demand and the exponential growth for wireless systems, which enables consumer to communicate in any place by means of information, has in turn led to the emergence of many portable wireless communication products. The present research works primarily targets to integrate as much as signal processing applications in a single portable device. Since integration through software applications compromises system speed, integration through hardware will be the better compliment. Software Defined Radio (SDR) Technology yields to achieve this small form factor system while keeping power consumption under the limit. SDR enables soft changeable system functionality, such as receiver demodulation technique .In this implementation two type modulation techniques are used, ASK and FSK. The flexibility of changing the receiver functionality in runtime is usually attained by FPGA. However, using a complete FPGA for reconfiguration of a particular functionality is not an efficient method in terms of power consumption and switching time. We proposed a SDR architecture using a recent advancement in FPGAs, called Partial Reconfiguration (PR). PR helps to change certain portion of FPGA, while the rest keeps functioning. It also reduces the total hardware usage and hence the power. The different demodulation technique and other signal processing application from an external memory unit can be loaded into FPGA PR modules while the other parts of FPGA doing a constant data processing.

KEYWORDS

Partial Reconfiguration in FPGA, Modulation Techniques, Wireless communication, CDMA, GSM, ASK, PSK, AM, FM

Original Source Link : http://aircconline.com/vlsics/V3N2/3212vlsics17.pdf

http://airccse.org/journal/vlsi/vol3.html

Design of Near-Threshold CMOS Logic Gates

Design of Near-Threshold CMOS Logic Gates

N. Geetha Rani1, N. Praveen Kumar2, Dr. B. Dr. B. Stephen Charles 3Dr. P. Chandrasekhar Reddy 4 S.Md.Imran Ali 5

1Assistant Professor, ECE Department, Stanley Stephen College of Engineering & Technology, Kurnool, A.P., India

2Assistant Professor, ECE Department, Stanley Stephen College of Engineering & Technology, Kurnool, A.P., India

3Professor, ECE Department, Stanley Stephen College of Engineering & Technology,Kurnool, A.P., India 

4Professor, ECE Department, JNTUH College of Engineering,Hyderabad, A.P., India

5 Assistant Professor, ECE Department, Stanley Stephen College of Engineering &Technology, Kurnool, A.P., India 

ABSTRACT

Numerous efforts have made to balance the tradeoff between power consumption, area and speed of a design. While studying the design at the two extreme ends of the design spectrum, namely the ultra-low power with acceptable performance at one end and high performance with power within limit at the other has not made. One solution to achieve the ultra-low power consumption is to operate the design in subthreshold region. The use of sub-threshold circuit designing in fast and energy efficient circuits is always needed in electronics industry especially in DSP, image processing and arithmetic units in microprocessors, where the low power is the primary concern and the delay can be tolerated. We design a simple CMOS inverter in weak inversion region (sub-threshold) and compare the power consumption with strong inversion region using Cadence 0.18µm Technology.

KEYWORDS:

Ultra low power, Sub-Threshold Region, CMOS

Original Scource Link : http://aircconline.com/vlsics/V3N2/3212vlsics16.pdf

http://airccse.org/journal/vlsi/vol3.html

THRESHOLD VOLTAGE CONTROL SCHEMES IN FINFETS

THRESHOLD VOLTAGE CONTROL SCHEMES IN FINFETS

V. Narendar1, Ramanuj Mishra2, Sanjeev Rai3, Nayana R4 and R. A. Mishra5

Department of Electronics & Communication Engineering, MNNIT-Allahabad Allahabad-211004, (U.P)-India

ABSTRACT

Conventionally polysilicon is used in MOSFETs for gate material. Doping of polysilicon and thus changing the workfunction is carried out to change the threshold voltage. Additionally polysilicon is not favourable as gate material for smaller dimensional devices because of its high thermal budget process and degradation due to the depletion of the doped polysilicon, thus metal gate is preferred over polysilicon. Control of workfunction in metal gate is a challenging task. The use of metal alloys as gate materials for variable gate workfunction has been already reported in literature. In this work various threshold voltage techniques has been analyzed and a novel aligned dual metal gate technique is proposed for threshold voltage control in FinFETs.

KEYWORDS

Dual-Metal gate (DMG), FinFET, Gate Workfunction, Independent-Gate (IG), Short channel Effects (SCEs), Threshold voltage (VT).

Original source Link : http://aircconline.com/vlsics/V3N2/3212vlsics15.pdf

http://airccse.org/journal/vlsi/vol3.html

DESIGN AND NOISE OPTIMIZATION OF RF LOW NOISE AMPLIFIER FOR IEEE STANDARD 802.11A WLAN

DESIGN AND NOISE OPTIMIZATION OF RF LOW NOISE AMPLIFIER FOR IEEE STANDARD 802.11A WLAN

Ravinder Kumar1 , Munish Kumar2, and Viranjay M. Srivastava1

1Department of Electronics and Communication Engineering, Jaypee University of Information Technology, Solan-173234, India.

2Department of Electronics and Communication Engineering, Guru Jambheshwar University of Science and Technology, Hisar-125001, India

ABSTRACT

Low noise amplifier is the front end block of radio-frequency receiver system. Its design required various characteristics such as power gain, noise figure, insertion losses and power consumption. In this paper we have proposed a single stage low noise amplifier design with high gain and low noise using inductive source degeneration topology for frequency range of 3 GHz to 7 GHz and also use the active biasing devices. A range of devices like inductors and capacitors are used to achieve 50 Ω input impedance with a low noise factor. The design process is simulated process is using Advance Design System (ADS) and implemented in TSMC 0.18 µm CMOS technology. A single stage low noise amplifier has a measured forward gain 25.4 dB and noise figure 2.2 dB at frequency 5.0 GHz.

KEYWORDS

Advanced design system, Low noise amplifier, Radio-frequency, Noise figure, Wireless network, CMOS, RF switch, VLSI

Original Source Link : http://aircconline.com/vlsics/V3N2/3212vlsics14.pdf

http://airccse.org/journal/vlsi/vol3.html

A Detailed Survey on VLSI Architectures for Lifting based DWT for efficient hardware implementation

A Detailed Survey on VLSI Architectures for Lifting based DWT for efficient hardware implementation

Usha Bhanu.N1 and Dr.A.Chilambuchelvan2

1Research Scholar, Anna University, Chennai-25, INDIA

2Professor, R.M.D. Engineering college ,Chennai-601 206 , INDIA

Abstract

Evaluating the previous work is an important part of developing new hardware efficient methods for the implementation of DWT through Lifting schemes. The aim of this paper is to give a review of VLSI architectures for efficient hardware implementation of wavelet lifting schemes. The inherent in place computation of lifting scheme has many advantages over conventional convolution based DWT. The architectures are represented in terms of parallel filter, row column, folded, flipping and recursive structures. The methods for scanning of images are the line-based and the block-based and their characteristics for the given application are given. The various architectures are analyzed in terms of hardware and timing complexity involved with the given size of input image and required levels of decomposition. This study is useful for deriving an efficient method for improving the speed and hardware complexities of existing architectures and to design a new hardware implementation of multilevel DWT using lifting schemes.

Keywords

Discrete Wavelet Transform, Lifting schemes, VLSI architectures, image compression.

Original Source Link : http://aircconline.com/vlsics/V3N2/3212vlsics13.pdf

http://airccse.org/journal/vlsi/vol3.html

FAULT SECURE ENCODER AND DECODER WITH CLOCK GATING

FAULT SECURE ENCODER AND DECODER WITH CLOCK GATING

N.Kapileswar1 and P.Vijaya Santhi2

Dept.of ECE,NRI Engineering College, Pothavarapadu,INDIA

Abstract:

This paper presents circuit design for a low power fault secure encoder and decoder system. Memory cells in logic circuits have been protected from soft errors for more than a decade due to increase in soft error rates. In this paper the circuitry around the memory block have been susceptible to soft errors and must be protected from faults. The proposed design uses error correcting codes and ring counter addressing scheme. In the ring counter several new clock gating techniques are proposed to reduce power consumption. A fault secure Encoder and Decoder error free low power logic circuits can be achieved by the proposed design. Simulation results show great improvement in power consumption. Fault secure Encoder and Decoder with clock gated by CG-element consumes approximately half the power of that consumed by the fault free circuit which doesn’t employ clock gating technique 

Keywords:

GC-element, first-in–first-out (FIFO), gated-clock, ring-counter, Double edge triggered(DET ) D flipflop(DFF ), encoder, decoder, detector, corrector.

Original Source Link : http://aircconline.com/vlsics/V3N2/3212vlsics12.pdf

http://airccse.org/journal/vlsi/vol3.html

An approach to design Flash Analog to Digital Converter for High Speed and Low power Applications

An approach to design Flash Analog to Digital Converter for High Speed and Low power Applications

P.RAJESWARI1 . R.RAMESH2., A.R.ASHWATHA3.

1PhD scholar, Telecommunication Engg Dept, Dayanada Sagar College of Engineering,Bangalore, India.

2Professor, E&C Dept, Saveetha engineering college, Chennai, India.

3Professor & Head, TCE Dept, Dayanada Sagar College of Engineering, Bangalore,India. 

ABSTRACT

This paper proposes the Flash ADC design using Quantized Differential Comparator and fat tree encoder. This approach explores the use of a systematically incorporated input offset voltage in a differential amplifier for quantizing the reference voltages necessary for Flash ADC architectures, therefore eliminating the need for a passive resistor array for the purpose. This approach allows very small voltage comparison and complete elimination of resistor ladder circuit. The thermometer code-to-binary code encoder has become the bottleneck of the ultra-high speed flash ADCs. In this paper, the fat tree thermometer code to-binary code encoder is used for the ultra high speed flash ADCs. The simulation and the implementation results shows that the fat tree encoder performs the commonly used ROM encoder in terms of speed and power for the 6 bit CMOS flash ADC case. The speed is improved by almost a factor of 2 when using the fat tree encoder, which in fact demonstrates the fat tree encoder and it is an effective solution for the bottleneck problem in ultra-high speed ADCs.The design has been carried out for the 0.18um technology using CADENCE tool.

KEYWORDS

TIQ, FAT TREE TC-BC ENCODER, CMOS, ANALOG TO DIGITAL CONVERTER.

Original Source Link  : http://aircconline.com/vlsics/V3N2/3212vlsics11.pdf

http://airccse.org/journal/vlsi/vol3.html

WISHBONE BUS ARCHITECTURE – A SURVEY AND COMPARISON

WISHBONE BUS ARCHITECTURE – A SURVEY AND COMPARISON

Mohandeep Sharma1 and Dilip Kumar2

1Department of VLSI Design, Center for Development of Advanced Computing, Mohali, India

2ACS - Division, Center for Development of Advanced Computing, Mohali, India

ABSTRACT

The performance of an on-chip interconnection architecture used for communication between IP cores depends on the efficiency of its bus architecture. Any bus architecture having advantages of faster bus clock speed, extra data transfer cycle, improved bus width and throughput is highly desirable for a low cost, reduced time-to-market and efficient System-on-Chip (SoC). This paper presents a survey of WISHBONE bus architecture and its comparison with three other on-chip bus architectures viz. Advanced Microcontroller Bus Architecture (AMBA) by ARM, CoreConnect by IBM and Avalon by Altera. The WISHBONE Bus Architecture by Silicore Corporation appears to be gaining an upper edge over the other three bus architecture types because of its special performance parameters like the use of flexible arbitration scheme and additional data transfer cycle (Read-Modify-Write cycle). Moreover, its IP Cores are available free for use requiring neither any registration nor any agreement or license. 

KEYWORDS

SoC buses, WISHBONE Bus, WISHBONE Interface

Original Source Link : http://aircconline.com/vlsics/V3N2/3212vlsics10.pdf

http://airccse.org/journal/vlsi/vol3.html

FPGA Implementation of ADPLL with Ripple Reduction Techniques

FPGA Implementation of ADPLL with Ripple Reduction Techniques

Manoj Kumar1 and Kusum Lata2

Department of Electronics and Communication Engineering, Indian Institute of Information Technology, Allahabad, INDIA

ABSTRACT

In this paper FPGA implementation of ADPLL using Verilog is presented. ADPLL with ripple reduction techniques is also simulated and implemented on FPGA. For simulation ISE Xilinx 10.1 CAD is used.Vertex5 FPGA (Field Programmable Gate Array) is used for implementation. ADPLL performance improvement, while using ripple reduction techniques is also discussed. The ADPLL is designed at the central frequency of 100 kHz. The frequency range of ADPLL is 0 kHz to 199 kHz. But when it is implemented with ripple reduction techniques, the frequency range observed is from 11 kHz to 216 kHz.

KEYWORDS: 

DCO, ADPLL, LOOP FILTER, PHASE DETECTOR

Original sourece Link : http://aircconline.com/vlsics/V3N2/3212vlsics09.pdf

http://airccse.org/journal/vlsi/vol3.html

SCOPE OF REVERSIBLE ENGINEERING AT GATE-LEVEL: FAULT-TOLERANT COMBINATIONAL ADDERS

SCOPE OF REVERSIBLE ENGINEERING AT GATE-LEVEL: FAULT-TOLERANT COMBINATIONAL ADDERS

M.Bharathi 1, K.Neelima2

1Assistant Professor, ECE Department, Sree Vidyanikethan Engineering College(Autonomous),Tirupati-517102, India

2Assistant Professor, ECE Department, Sree Vidyanikethan Engineering College(Autonomous),Tirupati-517102, India.

Abstract

Reversible engineering has been one of the thrust areas ensuring that continual process of the innovation trends that explore and sustain the resources of the nature. This reversible engineering is used in many fields like quantum computing, low power CMOS design, nanotechnology, optical information processing, digital signal processing, cryptography, etc. These are the digital domain implementations of Reversible and Fault-Tolerant logic gates. Any arbitrary Boolean function can be synthesized by using the proposed parity preserving reversible gates. Not only the possibility of detecting errors is induced inherently in the proposed high speed adders at their output side but also it allows any fault that affects no more than a single signal that is detectable. The fault tolerant reversible full adder circuits are realized by using two IG gates only. The derived fault tolerant full adder is used for designing other arithmetic- logic circuit by using it as fundamental building block. The proposed reversible gate is designed to have less hardware complexity and efficiecyt in terms of gate count, garbage outputs and constant input. In this paper, we design BCD adder using carry select logic, Carry-select and Bypass adders using FG gates, and newly designed TG gates.

Keywords

Delay, Miniaturization, Reversibility 

Original Source Link : http://aircconline.com/vlsics/V3N2/3212vlsics08.pdf

http://airccse.org/journal/vlsi/vol3.html

A Low Power High Bandwidth Four Quadrant Analog Multiplier in 32 NM CNFET Technology

A Low Power High Bandwidth Four Quadrant Analog Multiplier in 32 NM CNFET Technology 

Ishit Makwana1 and Vitrag Sheth2

1Dept. of Electrical & Electronics Engg, Birla Institute of Technology & Science (BITS) Pilani, Pilani, India

2Hewlett Packard Global Soft India Pvt. Ltd., Bangalore, India

ABSTRACT

Carbon Nanotube Field Effect Transistor (CNFET) is a promising new technology that overcomes several limitations of traditional silicon integrated circuit technology. In recent years, the potential of CNFET for analog circuit applications has been explored. This paper proposes a novel four quadrant analog multiplier design using CNFETs. The simulation based on 32nm CNFET technology shows that the proposed multiplier has very low harmonic distortion (<0.45%), large input range (±400mV), large bandwidth (~50GHz) and low power consumption (~247µW), while operating at a supply voltage of ±0.9V.

KEYWORDS

Carbon Nanotube FET, Nanoelectronics, Analog Integrated Circuits, Analog Multipliers, Low Power.

Original Source Link : http://aircconline.com/vlsics/V3N2/3212vlsics07.pdf

http://airccse.org/journal/vlsi/vol3.html

HIGH SPEED CONTINUOUS-TIME BANDPASS Σ∆ ADC FOR MIXED SIGNAL VLSI CHIPS

HIGH SPEED CONTINUOUS-TIME BANDPASS Σ∆ ADC FOR MIXED SIGNAL VLSI CHIPS

P.A.HarshaVardhini1 and Dr.M.MadhaviLatha2

1Ph.D Scholar, Dept. of ECE, J.N.T.U, Hyderabad, A.P, India.

2Professor and Head, Dept. of ECE, J.N.T.U, Hyderabad, A.P, India.

ABSTRACT

With the unremitting progress in VLSI technology, there is a commensurate increase in performance demand on analog to digital converter and are now being applied to wideband communication systems. sigma Delta (Σ∆) converter is a popular technique for obtaining high resolution with relatively small bandwidth. Σ∆ ADCs which trade sampling speed for resolution can benefit from the speed advantages of nm-CMOS technologies. This paper compares various Band pass sigma Delta ADC architectures, both continuous-time and discrete-time, in respect of power consumption and SNDR. Design of 2nd order multibit continuous time band pass Σ∆ modulator is discussed with the methods to resolve DAC non-idealities.

KEYWORDS

CMOS, Over sampling, Noise shaping, Sigma Delta Modulation, Bandpass Σ∆ modulator, Dynamic element matching, Data weighted averaging

Original Source Link : http://aircconline.com/vlsics/V3N2/3212vlsics06.pdf

http://airccse.org/journal/vlsi/vol3.html

Microcontroller Based Testing of Digital IP-Core

Microcontroller Based Testing of Digital IP-Core

Amandeep Singh1 and Balwinder Singh2

1-2Acadmic and Consultancy Services Division, Centre for Development of Advanced Computing(C-DAC), Mohali, India

ABSTRACT

Testing core based System on Chip [1] is a challenge for the test engineers. To test the complete SOC at one time with maximum fault coverage, test engineers prefer to test each IP-core separately. At speed testing using external testers is more expensive because of gigahertz processor. The purpose of this paper is to develop cost efficient and flexible test methodology for testing digital IP-cores [2]. The prominent feature of the approach is to use microcontroller to test IP-core. The novel feature is that there is no need of test pattern generator and output response analyzer as microcontroller performs the function of both. This approach has various advantages such as at speed testing, low cost, less area overhead and greater flexibility since most of the testing process is based on software.

KEYWORDS

Microcontroller, FPGA, Testing, TMR, SOC

Original Source Link : http://aircconline.com/vlsics/V3N2/3212vlsics05.pdf

http://airccse.org/journal/vlsi/vol3.html