FPGA Implementation of ADPLL with Ripple Reduction Techniques

FPGA Implementation of ADPLL with Ripple Reduction Techniques

Manoj Kumar1 and Kusum Lata2

Department of Electronics and Communication Engineering, Indian Institute of Information Technology, Allahabad, INDIA

ABSTRACT

In this paper FPGA implementation of ADPLL using Verilog is presented. ADPLL with ripple reduction techniques is also simulated and implemented on FPGA. For simulation ISE Xilinx 10.1 CAD is used.Vertex5 FPGA (Field Programmable Gate Array) is used for implementation. ADPLL performance improvement, while using ripple reduction techniques is also discussed. The ADPLL is designed at the central frequency of 100 kHz. The frequency range of ADPLL is 0 kHz to 199 kHz. But when it is implemented with ripple reduction techniques, the frequency range observed is from 11 kHz to 216 kHz.

KEYWORDS: 

DCO, ADPLL, LOOP FILTER, PHASE DETECTOR

Original sourece Link : http://aircconline.com/vlsics/V3N2/3212vlsics09.pdf

http://airccse.org/journal/vlsi/vol3.html