WISHBONE BUS ARCHITECTURE – A SURVEY AND COMPARISON
Mohandeep Sharma1 and Dilip Kumar2
1Department of VLSI Design, Center for Development of Advanced Computing, Mohali, India
2ACS - Division, Center for Development of Advanced Computing, Mohali, India
ABSTRACT
The performance of an on-chip interconnection architecture used for communication between IP cores depends on the efficiency of its bus architecture. Any bus architecture having advantages of faster bus clock speed, extra data transfer cycle, improved bus width and throughput is highly desirable for a low cost, reduced time-to-market and efficient System-on-Chip (SoC). This paper presents a survey of WISHBONE bus architecture and its comparison with three other on-chip bus architectures viz. Advanced Microcontroller Bus Architecture (AMBA) by ARM, CoreConnect by IBM and Avalon by Altera. The WISHBONE Bus Architecture by Silicore Corporation appears to be gaining an upper edge over the other three bus architecture types because of its special performance parameters like the use of flexible arbitration scheme and additional data transfer cycle (Read-Modify-Write cycle). Moreover, its IP Cores are available free for use requiring neither any registration nor any agreement or license.
KEYWORDS
SoC buses, WISHBONE Bus, WISHBONE Interface
Original Source Link : http://aircconline.com/vlsics/V3N2/3212vlsics10.pdf
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