FAULT SECURE ENCODER AND DECODER WITH CLOCK GATING
N.Kapileswar1 and P.Vijaya Santhi2
Dept.of ECE,NRI Engineering College, Pothavarapadu,INDIA
Abstract:
This paper presents circuit design for a low power fault secure encoder and decoder system. Memory cells in logic circuits have been protected from soft errors for more than a decade due to increase in soft error rates. In this paper the circuitry around the memory block have been susceptible to soft errors and must be protected from faults. The proposed design uses error correcting codes and ring counter addressing scheme. In the ring counter several new clock gating techniques are proposed to reduce power consumption. A fault secure Encoder and Decoder error free low power logic circuits can be achieved by the proposed design. Simulation results show great improvement in power consumption. Fault secure Encoder and Decoder with clock gated by CG-element consumes approximately half the power of that consumed by the fault free circuit which doesn’t employ clock gating technique
Keywords:
GC-element, first-in–first-out (FIFO), gated-clock, ring-counter, Double edge triggered(DET ) D flipflop(DFF ), encoder, decoder, detector, corrector.
Original Source Link : http://aircconline.com/vlsics/V3N2/3212vlsics12.pdf
No comments:
Post a Comment