Design of Near-Threshold CMOS Logic Gates
N. Geetha Rani1, N. Praveen Kumar2, Dr. B. Dr. B. Stephen Charles 3Dr. P. Chandrasekhar Reddy 4 S.Md.Imran Ali 5
1Assistant Professor, ECE Department, Stanley Stephen College of Engineering & Technology, Kurnool, A.P., India
2Assistant Professor, ECE Department, Stanley Stephen College of Engineering & Technology, Kurnool, A.P., India
3Professor, ECE Department, Stanley Stephen College of Engineering & Technology,Kurnool, A.P., India
4Professor, ECE Department, JNTUH College of Engineering,Hyderabad, A.P., India
5 Assistant Professor, ECE Department, Stanley Stephen College of Engineering &Technology, Kurnool, A.P., India
ABSTRACT
Numerous efforts have made to balance the tradeoff between power consumption, area and speed of a design. While studying the design at the two extreme ends of the design spectrum, namely the ultra-low power with acceptable performance at one end and high performance with power within limit at the other has not made. One solution to achieve the ultra-low power consumption is to operate the design in subthreshold region. The use of sub-threshold circuit designing in fast and energy efficient circuits is always needed in electronics industry especially in DSP, image processing and arithmetic units in microprocessors, where the low power is the primary concern and the delay can be tolerated. We design a simple CMOS inverter in weak inversion region (sub-threshold) and compare the power consumption with strong inversion region using Cadence 0.18µm Technology.
KEYWORDS:
Ultra low power, Sub-Threshold Region, CMOS
Original Scource Link : http://aircconline.com/vlsics/V3N2/3212vlsics16.pdf
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