An approach to design Flash Analog to Digital Converter for High Speed and Low power Applications
P.RAJESWARI1 . R.RAMESH2., A.R.ASHWATHA3.
1PhD scholar, Telecommunication Engg Dept, Dayanada Sagar College of Engineering,Bangalore, India.
2Professor, E&C Dept, Saveetha engineering college, Chennai, India.
3Professor & Head, TCE Dept, Dayanada Sagar College of Engineering, Bangalore,India.
ABSTRACT
This paper proposes the Flash ADC design using Quantized Differential Comparator and fat tree encoder. This approach explores the use of a systematically incorporated input offset voltage in a differential amplifier for quantizing the reference voltages necessary for Flash ADC architectures, therefore eliminating the need for a passive resistor array for the purpose. This approach allows very small voltage comparison and complete elimination of resistor ladder circuit. The thermometer code-to-binary code encoder has become the bottleneck of the ultra-high speed flash ADCs. In this paper, the fat tree thermometer code to-binary code encoder is used for the ultra high speed flash ADCs. The simulation and the implementation results shows that the fat tree encoder performs the commonly used ROM encoder in terms of speed and power for the 6 bit CMOS flash ADC case. The speed is improved by almost a factor of 2 when using the fat tree encoder, which in fact demonstrates the fat tree encoder and it is an effective solution for the bottleneck problem in ultra-high speed ADCs.The design has been carried out for the 0.18um technology using CADENCE tool.
KEYWORDS
TIQ, FAT TREE TC-BC ENCODER, CMOS, ANALOG TO DIGITAL CONVERTER.
Original Source Link : http://aircconline.com/vlsics/V3N2/3212vlsics11.pdf
No comments:
Post a Comment