Pipelining Architecture of AES Encryption and Key Generation with Search Based Memory

 International journal of VLSI design & Communication Systems (VLSICS)

ISSN : 0976 - 1357  (Online); 0976 - 1527(print)

Pipelining Architecture of AES Encryption and Key Generation with Search Based Memory

Subashri T1, Arunachalam R2, Gokul Vinoth Kumar B3, Vaidehi V4

Abstract.

A high speed security algorithm is always important for wired/wireless environment. The symmetric block cipher plays a major role in the bulk data encryption. One of the best existing symmetric security algorithms to provide data security is AES. AES has the advantage of being implemented in both hardware and software. Hardware implementation of the AES has the advantage of increased throughput and offers better security. Search based S-box architecture has been proposed in this paper to reduce the constraint in the hardware resources. The pipelined architecture of the AES algorithm is proposed in order to increase the throughput of the algorithm. Moreover the key schedule algorithm of the AES encryption is pipelined to get the speedup.

Keywords

AES pipelining, Key pipelining, Search Based Memory, VLSI. 

Original Source URL: https://aircconline.com/vlsics/V1N4/1210vlsics05.pdf

Volume URL: https://airccse.org/journal/vlsi/vol1.html

International journal of VLSI design & Communication Systems (VLSICS)

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International journal of VLSI design & Communication Systems (VLSICS)

ISSN : 0976 - 1357  (Online); 0976 - 1527(print)

Submission Deadline : September 06, 2026

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International Journal of VLSI Design & Communication Systems

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International journal of VLSI design & Communication Systems (VLSICS)

 Call For Research Papers..!!

International journal of VLSI design & Communication Systems (VLSICS)

ISSN : 0976 - 1357  (Online); 0976 - 1527(print)

Submission Deadline : September 06, 2026

For More details visit here : http://airccse.org/journal/vlsi/vlsics.html

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 International journal of VLSI design & Communication Systems (VLSICS)

ISSN : 0976 - 1357  (Online); 0976 - 1527(print)

DYNAMIC TASK SCHEDULING ON MULTICORE AUTOMOTIVE ECUS

Geetishree Mishra1, K S Gurumurthy2

1BMS College of Engineering, Bangalore, India,

2Reva Intitute of Technology, Bangalore, India 

ABSTRACT

Automobile manufacturers are controlled by stringent govt. regulations for safety and fuel emissions and

motivated towards adding more advanced features and sophisticated applications to the existing electronic

system. Ever increasing customer’s demands for high level of comfort also necessitate providing even more

sophistication in vehicle electronics system. All these, directly make the vehicle software system more

complex and computationally more intensive. In turn, this demands very high computational capability of

the microprocessor used in electronic control unit (ECU). In this regard, multicore processors have

already been implemented in some of the task rigorous ECUs like, power train, image processing and

infotainment. To achieve greater performance from these multicore processors, parallelized ECU software

needs to be efficiently scheduled by the underlaying operating system for execution to utilize all the

computational cores to the maximum extent possible and meet the real time constraint. In this paper, we

propose a dynamic task scheduler for multicore engine control ECU that provides maximum CPU

utilization, minimized preemption overhead, minimum average waiting time and all the tasks meet their

real time deadlines while compared to the static priority scheduling suggested by Automotive Open Systems

Architecture (AUTOSAR).

KEYWORDS

OEM, ECU, Multicore, Scheduling, AUTOSAR

Original Source URL: https://aircconline.com/vlsics/V5N6/5614vlsi01.pdf

Volume URL: https://airccse.org/journal/vlsi/vol5.html

12th International Conference on VLSI and Applications (VLSIA 2026)

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Call For Research Papers..!!

International journal of VLSI design & Communication Systems (VLSICS)

ISSN : 0976 - 1357  (Online); 0976 - 1527(print)

Submission Deadline : September 06, 2026

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International journal of VLSI design & Communication Systems (VLSICS)

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Call For Research Articles..!!!

International journal of VLSI design & Communication Systems (VLSICS)

ISSN : 0976 - 1357 (Online); 0976 - 1527(print)

Submission Deadline : August 30, 2026

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