International journal of VLSI design & Communication Systems (VLSICS)

 #CommunicationSystems #WirelessCommunication #DigitalCommunication #Telecommunication #CommunicationEngineering #SignalProcessing #WirelessNetworks #5GTechnology #6GTechnology #OpticalCommunication #SatelliteCommunication #NetworkTechnology #RFCommunication #MobileCommunication #DataCommunication #InformationTheory #ModulationTechniques #AntennaDesign #IoTCommunication #CommunicationNetworks #BroadbandCommunication #SmartCommunications #EmergingTechnologies #TelecomEngineering #CommunicationResearc

Call For Papers.!!!

International journal of VLSI design & Communication Systems (VLSICS)

ISSN : 0976 - 1357  (Online); 0976 - 1527(print)

Submission Deadline : October 17, 2026

For More details visit here : http://airccse.org/journal/vlsi/vlsics.html

Submission System Link: https://airccse.com/submissioncs/home.html

Contact Us

Here's where you can reach us : vlsicsjournal@airccse.org or vlsics@aircconline.com or vlsicsjournal910@gmail.com

Single bit full adder design using 8 transistors with novel 3 transistors XNOR gate

 International journal of VLSI design & Communication Systems (VLSICS)

ISSN : 0976 - 1357  (Online); 0976 - 1527(print)

Single bit full adder design using 8 transistors with novel 3 transistors XNOR gate

Manoj Kumar1, Sandeep K. Arya1 and Sujata Pandey2 

Abstract:

In present work a new XNOR gate using three transistors has been presented, which shows power dissipation of 550.7272µW in 0.35µm technology with supply voltage of 3.3V. Minimum level for high output of 2.05V and maximum level for low output of 0.084V have been obtained. A single bit full adder using eight transistors has been designed using proposed XNOR cell, which shows power dissipation of 581.542µW. Minimum level for high output of 1.97V and maximum level for low output of 0.24V is obtained for sum output signal. For carry signal maximum level for low output of 0.32V and minimum level for high output of 3.2V have been achieved. Simulations have been performed by using SPICE based on TSMC 0.35µm CMOS technology. Power consumption of proposed XNOR gate and full adder has been compared with earlier reported circuits and proposed circuit’s shows better performance in terms of power consumption and transistor count.

Keywords:

CMOS, exclusive-OR (XOR), exclusive-NOR (XNOR), full adder, low power, pass transistor logic. 

Article URL : https://aircconline.com/vlsics/V2N4/2411vlsics05.pdf

For More Details : https://airccse.org/journal/vlsi/vlsics.html

International journal of VLSI design & Communication Systems (VLSICS)

 #VLSI #VLSIDesign #VLSICircuits #VLSITechnology #VLSIEngineering #IntegratedCircuits #ICDesign #DigitalDesign #AnalogDesign #Semiconductor #Microelectronics #ChipDesign #ASICDesign #FPGA #SystemOnChip #SoC #ElectronicDesign #CircuitDesign #EmbeddedSystems #Nanoelectronics

Call For Papers.!!!

International journal of VLSI design & Communication Systems (VLSICS)

ISSN : 0976 - 1357  (Online); 0976 - 1527(print)

Submission Deadline : October 17, 2026

For More details visit here : http://airccse.org/journal/vlsi/vlsics.html

Submission System Link: https://airccse.com/submissioncs/home.html

Contact Us

Here's where you can reach us : vlsicsjournal@airccse.org or vlsics@aircconline.com or vlsicsjournal910@gmail.com 

International journal of VLSI design & Communication Systems (VLSICS)

 #CommunicationSystems #DigitalCommunication #WirelessCommunication #Telecommunication #DataCommunication #SignalProcessing #CommunicationEngineering #NetworkCommunication #SatelliteCommunication #OpticalCommunication #MobileCommunication #5GTechnology #6GTechnology #IoTCommunication #RFCommunication #InformationTheory #SignalTransmission #WirelessNetworks #CommunicationTechnology #ElectronicsCommunication

International journal of VLSI design & Communication Systems (VLSICS)

ISSN : 0976 - 1357  (Online); 0976 - 1527(print)

Submission Deadline : October 17, 2026

For More details visit here : http://airccse.org/journal/vlsi/vlsics.html

Submission System Link: https://airccse.com/submissioncs/home.html

Contact Us

Here's where you can reach us : vlsicsjournal@airccse.org or vlsics@aircconline.com or vlsicsjournal910@gmail.com

International journal of VLSI design & Communication Systems (VLSICS)

 #VLSI #VLSIDesign #VLSICircuits #VLSITechnology #VLSIEngineering #IntegratedCircuits #ICDesign #DigitalDesign #AnalogDesign #Semiconductor #Microelectronics #ChipDesign #ASICDesign #FPGA #SystemOnChip #SoC #ElectronicDesign #CircuitDesign #EmbeddedSystems #Nanoelectronics

Call For Papers..!!!

International journal of VLSI design & Communication Systems (VLSICS)

ISSN : 0976 - 1357  (Online); 0976 - 1527(print)

Submission Deadline : October 10, 2026

For More details visit here : http://airccse.org/journal/vlsi/vlsics.html

Submission System Link: https://airccse.com/submissioncs/home.html

Contact Us

Here's where you can reach us : vlsicsjournal@airccse.org or vlsics@aircconline.com or vlsicsjournal910@gmail.com 

A TECHNIQUE FOR DESIGNING HIGH SPEED NOISE IMMUNE CMOS DOMINO HIGH FAN-IN CIRCUITS IN 16nm TECHNOLOGY

 International journal of VLSI design & Communication Systems (VLSICS)

ISSN : 0976 - 1357  (Online); 0976 - 1527(print)

A TECHNIQUE FOR DESIGNING HIGH SPEED NOISE IMMUNE CMOS DOMINO HIGH FAN-IN CIRCUITS IN 16nm TECHNOLOGY

P. Koti Lakshmi1 and Prof. Rameshwar Rao2

ABSTRACT

Dynamic logic circuits provide more compact designs with faster switching speeds and low power consumption compared with the other CMOS design styles. Domino logic overcomes the difficulties in dynamic circuits such as charge sharing and cascading. In this paper we are proposing a wide f
an-in circuit with increased switching speed and noise immunity. Speed is achieved by quickly removing the charge on the dynamic node during evaluation phase, compared to the other circuits. The design also offers less Power Delay Product (PDP). The design is exercised for 20% variation in supply voltage. The design shows a 1.83% improvement in Average Noise Threshold Energy (ANTE). Using the proposed technique an Octal-to-binary encoder is designed and simulated.

KEYWORDS

Low PDP design, High speed OR gate, Octal-binary Encoder, Domino OR gate, Low power design, ANTE. 

Article URL : https://aircconline.com/vlsics/V6N5/6515vlsi05.pdf

For More details visit here : http://airccse.org/journal/vlsi/vlsics.html

14th International Conference on Signal, Image Processing and Pattern Recognition (SIPP 2026)

 #ImageProcessing #DigitalArt #CreativeTech #AIArt #FutureIsNow #Photography #TechInnovation #VisualEffects #ModernArt #DeepLearning #ComputerVision #ArtAndTechnology #GenerativeArt #DigitalCreator #ImageManipulation #PhotoManipulation #CreativeCoding #ArtOfCode #VisualStorytelling #TechForGood #InstaTech #DigitalTransformation #AICommunity #VisualDesign #TechTrends #LearnAI #CreativeAI #ExploreTech #ImageMagic #VisualJourney

14th International Conference on Signal, Image Processing and Pattern Recognition (SIPP 202
6)

November 21 ~ 22, 2026, London, United Kingdom

https://ccsit2026.org/sipp/index

Submission Deadline:  October 10, 2026

Contact Us : sipp@ccsit2026.org

Paper Submission Link : https://ccsit2026.org/submission/index.php