International journal of VLSI design & Communication Systems (VLSICS)
ISSN : 0976 - 1357 (Online); 0976 - 1527(print)
Single bit full adder design using 8 transistors with novel 3 transistors XNOR gate
Manoj Kumar1, Sandeep K. Arya1 and Sujata Pandey2
Abstract:
In present work a new XNOR gate using three transistors has been presented, which shows power dissipation of 550.7272µW in 0.35µm technology with supply voltage of 3.3V. Minimum level for high output of 2.05V and maximum level for low output of 0.084V have been obtained. A single bit full adder using eight transistors has been designed using proposed XNOR cell, which shows power dissipation of 581.542µW. Minimum level for high output of 1.97V and maximum level for low output of 0.24V is obtained for sum output signal. For carry signal maximum level for low output of 0.32V and minimum level for high output of 3.2V have been achieved. Simulations have been performed by using SPICE based on TSMC 0.35µm CMOS technology. Power consumption of proposed XNOR gate and full adder has been compared with earlier reported circuits and proposed circuit’s shows better performance in terms of power consumption and transistor count.
Keywords:
CMOS, exclusive-OR (XOR), exclusive-NOR (XNOR), full adder, low power, pass transistor logic.
Article URL : https://aircconline.com/vlsics/V2N4/2411vlsics05.pdf
For More Details : https://airccse.org/journal/vlsi/vlsics.html
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