Friday, 18 September 2026

VALID IRREVERSIBLE RESOLUTION RATE: AN EVENT-LEVEL ENERGY METRIC FOR STABILIZED DECISIONS IN VLSI AND EDGE-AI HARDWARE

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**Current Issue**




VALID IRREVERSIBLE RESOLUTION RATE: AN EVENT-LEVEL ENERGY METRIC FOR STABILIZED DECISIONS IN VLSI AND EDGE-AI HARDWARE


Martin Petrásek


ABSTRACT

Energy efficiency in VLSI and edge-AI hardware is commonly reported as OPS/W, TOPS/W, or energy per inference. These metrics quantify activity or completed tasks, but they do not require an explicit physical decision boundary, retention window, rejection rule, or stabilization ledger. This article develops the Valid Irreversible Resolution Rate (VIRR), an event-level metric that counts accepted stable irreversible outcomes per supplied joule. The framework separates full physical VIRR, task-level VIRR, and operationderived estimates to prevent overclaiming from incomplete public data. Reproducible demonstrations convert 27 MLPerf Tiny v1.3 power results into task-level outcomes/J, compute a VIRRpulse proxy from public CoO/Nb:SrTiO3 memristor data, and include a controlled full-pipeline Langevin validation with 

forward/reverse work and entropy-production ledgers. At a 5% update threshold, the resistance-based device-level VIRR estimate for 1.2 V pulses is 4.4× higher than for 1.4 V pulses.


KEYWORDS

event-level energy efficiency, irreversible decisions, information thermodynamics, VLSI, edge AI


For More Details Visit Here :

https://aircconline.com/vlsics/V17N4/17426vlsi01.pdf


Paper Submission URL : https://airccse.com/submissioncs/home.html


Thursday, 17 September 2026

International journal of VLSI design & Communication Systems (VLSICS)

 #VLSICS #ImageProcessing #DigitalArt #CreativeTech #AIArt #FutureIsNow #Photography #TechInnovation #VisualEffects #ModernArt #DeepLearning #ComputerVision #ArtAndTechnology #GenerativeArt #DigitalCreator #ImageManipulation #PhotoManipulation #CreativeCoding #ArtOfCode #VisualStorytelling #TechForGood #InstaTech #DigitalTransformation #AICommunity #VisualDesign #TechTrends #LearnAI #CreativeAI #ExploreTech #ImageMagic 


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***Citation - 3060  h-index - 28  i10-index - 93***


International journal of VLSI design & Communication Systems (VLSICS)


ISSN : 0976 - 1357  (Online); 0976 - 1527(print)


Submission Deadline : September 20, 2026


For More details visit here : http://airccse.org/journal/vlsi/vlsics.html


Submission System Link: https://airccse.com/submissioncs/home.html


Wednesday, 16 September 2026

International journal of VLSI design & Communication Systems (VLSICS)

 Call For Papers..!!!


***H-Index - 28***


International journal of VLSI design & Communication Systems (VLSICS)


ISSN : 0976 - 1357  (Online); 0976 - 1527(print)


Submission Deadline : September 20, 2026


For More details visit here : http://airccse.org/journal/vlsi/vlsics.html


Submission System Link: https://airccse.com/submissioncs/home.html


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Here's where you can reach us : vlsicsjournal@airccse.org or vlsics@aircconline.com or vlsicsjournal910@gmail.com


#VLSICS #ImageProcessing #DigitalArt #CreativeTech #AIArt #FutureIsNow #Photography #TechInnovation #VisualEffects #ModernArt #DeepLearning #ComputerVision #ArtAndTechnology #GenerativeArt #DigitalCreator #ImageManipulation #PhotoManipulation #CreativeCoding #ArtOfCode #VisualStorytelling #TechForGood #InstaTech #DigitalTransformation #AICommunity #VisualDesign #TechTrends #LearnAI #CreativeAI #ExploreTech #ImageMagic 


Friday, 11 September 2026

International journal of VLSI design & Communication Systems (VLSICS)

 Call For Research Articles..!!!


International journal of VLSI design & Communication Systems (VLSICS)


ISSN : 0976 - 1357  (Online); 0976 - 1527(print)


Submission Deadline : September 13, 2026


For More details visit here : http://airccse.org/journal/vlsi/vlsics.html


Submission System Link: https://airccse.com/submissioncs/home.html


Contact Us

Here's where you can reach us : vlsicsjournal@airccse.org or vlsics@aircconline.com


#VLSICS #ImageProcessing #DigitalArt #CreativeTech #AIArt #FutureIsNow #Photography #TechInnovation #VisualEffects #ModernArt #DeepLearning #ComputerVision #ArtAndTechnology #GenerativeArt #DigitalCreator #ImageManipulation #PhotoManipulation #CreativeCoding #ArtOfCode #VisualStorytelling #TechForGood #InstaTech #DigitalTransformation #AICommunity #VisualDesign #TechTrends #LearnAI #CreativeAI #ExploreTech #ImageMagic


Thursday, 10 September 2026

International journal of VLSI design & Communication Systems (VLSICS)

 #VLSICS #ImageProcessing #DigitalArt #CreativeTech #AIArt #FutureIsNow #Photography #TechInnovation #VisualEffects #ModernArt #DeepLearning #ComputerVision #ArtAndTechnology #GenerativeArt #DigitalCreator #ImageManipulation #PhotoManipulation #CreativeCoding #ArtOfCode #VisualStorytelling #TechForGood #InstaTech #DigitalTransformation #AICommunity #VisualDesign #TechTrends #LearnAI #CreativeAI #ExploreTech #ImageMagic


Call For Research Articles..!!!


International journal of VLSI design & Communication Systems (VLSICS)


ISSN : 0976 - 1357  (Online); 0976 - 1527(print)


Submission Deadline : September 13, 2026


For More details visit here : http://airccse.org/journal/vlsi/vlsics.html


Submission System Link: https://airccse.com/submissioncs/home.html


Contact Us

Here's where you can reach us : vlsicsjournal@airccse.org or vlsics@aircconline.com 

Wednesday, 9 September 2026

Pipelining Architecture of AES Encryption and Key Generation with Search Based Memory

 International journal of VLSI design & Communication Systems (VLSICS)


ISSN : 0976 - 1357  (Online); 0976 - 1527(print)



Pipelining Architecture of AES Encryption and Key Generation with Search Based Memory


Subashri T1, Arunachalam R2, Gokul Vinoth Kumar B3, Vaidehi V4


Abstract.

A high speed security algorithm is always important for wired/wireless environment. The symmetric block cipher plays a major role in the bulk data encryption. One of the best existing symmetric security algorithms to provide data security is AES. AES has the advantage of being implemented in both hardware and software. Hardware implementation of the AES has the advantage of increased throughput and offers better security. Search based S-box architecture has been proposed in this paper to reduce the constraint in the hardware resources. The pipelined architecture of the AES algorithm is proposed in order to increase the throughput of the algorithm. Moreover the key schedule algorithm of the AES encryption is pipelined to get the speedup.


Keywords

AES pipelining, Key pipelining, Search Based Memory, VLSI. 



Original Source URL: https://aircconline.com/vlsics/V1N4/1210vlsics05.pdf


Volume URL: https://airccse.org/journal/vlsi/vol1.html


Friday, 4 September 2026

International journal of VLSI design & Communication Systems (VLSICS)

 #VLSI #VLSIDesign #VLSIDesigning #VLSIEngineering #ASIC #FPGA #RTLDesign #Verilog #SystemVerilog #SoC #Semiconductor #ChipDesign #ICDesign #DigitalDesign #EmbeddedSystems #CommunicationSystems #WirelessCommunication #5G #6G #IoT #MIMO #MassiveMIMO #WirelessTechnology #SignalProcessing #Telecommunications #RF #RFDesign #SatelliteCommunication #OpticalCommunication



International journal of VLSI design & Communication Systems (VLSICS)


ISSN : 0976 - 1357  (Online); 0976 - 1527(print)


Submission Deadline : September 06, 2026


For More details visit here : http://airccse.org/journal/vlsi/vlsics.html


Submission System Link: https://airccse.com/submissioncs/home.html


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Here's where you can reach us : vlsicsjournal@airccse.org or vlsics@aircconline.com


International Journal of VLSI Design & Communication Systems

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