Comparative Performance Analysis of XORXNOR Function Based High-Speed CMOS Full Adder Circuits For Low Voltage VLSI Design
Subodh Wairya1, Rajendra Kumar Nagaria2 and Sudarshan Tiwari2
1Department of Electronics Engineering, Institute of Engineering & Technology (I.E.T),Lucknow, India, 226021
2Department of ECED, Motilal Nehru National Institute of Technology (MNNIT), Allahabad, India, 211004
ABSTRACT
This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T)” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as it lowers power consumption by using XOR (3T) logic circuits. Gate Diffusion Input (GDI) technique of low-power digital combinatorial circuit design is also described. This technique helps in reducing the power consumption and the area of digital circuits while maintaining low complexity of logic design. This paper analyses, evaluates and compares the performance of various adder circuits. Several simulations conducted using different voltage supplies, load capacitors and temperature variation demonstrate the superiority of the XOR (3T) based full adder designs in term of delay, power and power delay product (PDP) compared to the other full adder circuits. Simulation results illustrate the superiority of the designed adder circuits against the conventional CMOS, TG and Hybrid full adder circuits in terms of power, delay and power delay product (PDP).
KEYWORDS
Hybrid full adder, XOR-XNOR circuit, High Speed, Low Power, Very Large Scale Integrated (VLSI)Circuits,
Original Scource Link : http://aircconline.com/vlsics/V3N2/3212vlsics19.pdf
No comments:
Post a Comment