STATIC NOISE MARGIN OPTIMIZED 11NM SHORTED-GATE AND INDEPENDENT-GATE LOW POWER 6T FINFET SRAM TOPOLOGIES

STATIC NOISE MARGIN OPTIMIZED 11NM SHORTED-GATE AND INDEPENDENT-GATE LOW POWER 6T FINFET SRAM TOPOLOGIES

DustenVernor, Santosh Koppa and Eugene John

Department of Electrical andComputer Engineering, University of Texas at San Antonio, Texas, USA

ABSTRACT

This paper investigates the leakage current, static noise margin (SNM), delay and energy consumption of a 6 transistor FinFET based static random-access memory (SRAM) cell due to the variation in design and operating parameters of the SRAM cell. The SRAM design and operating parameters considered in this investigation are transistor sizing, supply voltage, word-line voltage, temperature and PFET and NFET back gate biasing. This investigation is performed using a 11nm FinFET shorted gate and low power technology models. Based on the investigation results, we propose a robust 6 transistor SRAM cells with optimized performance using shorted gate and independent gate low power FinFET models. By optimizing the design parameters of the cell, the shorted-gate design shows an improvement of read SNM of 261.56mV and an improvement of hold SNM of 87.68mV when compared to a shorted-gate cell with standard design parameters. The low-power design shows an improvement of read SNM of 146.18mV and a marginal decrease in hold SNM of 22.84mV when compared to a low-power cell with standard design parameters. Both the cells with the new optimized design parameters are shown to improve the overall SNM of the cells with minimal impact on the subthreshold leakage currents, performance and energy consumption.

KEYWORDS

SRAM, Leakage Power, Write Delay, Read Delay, FinFET, Static Noise Margin, SNM, Back GateBiasing.

Original Source Link : http://aircconline.com/vlsics/V9N5/9518vlsi01.pdf

http://airccse.org/journal/vlsi/current.html