EFFICIENT IMPLEMENTATION OF 16-BIT MULTIPLIER-ACCUMULATOR USING RADIX-2 MODIFIED BOOTH ALGORITHM AND SPST ADDER USING VERILOG

EFFICIENT IMPLEMENTATION OF 16-BIT MULTIPLIER-ACCUMULATOR USING RADIX-2 MODIFIED BOOTH ALGORITHM AND SPST ADDER USING VERILOG

Addanki Purna Ramesh1, Dr.A.V. N. Tilak2 and Dr.A.M.Prasad3

1Department of ECE, Sri Vasavi Engineering College, Pedatadepalli, Tadepalligudem, India

2Department of ECE, Gudlavalleru Engineering College, Gudlavalleru, India

3Department of ECE, UCEK, JNTU, Kakinada, India

ABSTRACT

In this paper, we propose a new multiplier-and-accumulator (MAC) architecture for low power and high speed arithmetic. High speed and low power MAC units are required for applications of digital signal processing like Fast Fourier Transform, Finite Impulse Response filters, convolution etc. For improving the speed and reducing the dynamic power, there is a need to reduce the glitches (1 to 0 transition) and spikes (0 to 1 transition). Adder designed using spurious power suppression technique (SPST) avoids the unwanted glitches and spikes, thus minimizing the switching power dissipation and hence the dynamic power. Radix -2 modified booth algorithm reduces the number of partial products to half by grouping of bits from the multiplier term, which improves the speed. The proposed radix-2 modified Booth algorithm

MAC with SPST gives a factor of 5 less delay and 7% less power consumption as compared to array MAC

KEYWORDS

Radix -2 modified booth algorithm, Digital signal processing, spurious power suppression Technique, Verilog.

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