DESIGN AND PERFORMANCE ANALYSIS OF ULTRA LOW POWER 6T SRAM USING ADIABATIC TECHNIQUE

DESIGN AND PERFORMANCE ANALYSIS OF ULTRA LOW POWER 6T SRAM USING ADIABATIC TECHNIQUE

Mr. Sunil Jadav1, Mr. Vikrant2, Dr. Munish Vashisath3

2PG Student, Electrical & Electronics Engineering Dept. YMCAUS&T, Faridabad,Haryana

1,3Faculty, Electrical & Electronics Engineering Dept. YMCAUS&T, Faridabad, Haryana

ABSTRACT: 

Power consumption has become a critical concern in both high performance and portable applications. Methods for power reduction based on the application of adiabatic techniques to CMOS circuits have recently come under renewed investigation. In thermodynamics, an adiabatic energy transfer through a dissipative medium is one in which losses are made arbitrarily small by causing the transfer to occur sufficiently slowly. In this work adiabatic technique is used for reduction of average power

dissipation. Simulation of 6T SRAM cell has been done for 180nm CMOS technology. It shows that average power dissipation is reduced up to 75% using adiabatic technique and also shows the effect on static noise margin.

Keywords

Adiabatic Logic, Average Power dissipation, Static Noise Margin

Original source Link : http://aircconline.com/vlsics/V3N3/3312vlsics09.pdf

http://airccse.org/journal/vlsi/vol3.html