Design of Efficient Adder Circuits Using PROPOSED PARITY PRESERVING GATE (PPPG)
Krishna Murthy M, Gayatri G, Manoj Kumar R
Department of ECE, MVGRCE, Vizianagaram, Andhra Pradesh
ABSTRACT
Reversible logic is becoming an important research area which aims mainly to reduce power dissipation during computing. In this paper we introduce a new parity preserving reversible gate PPPG (a 5x5 gate). This gate is universal in the sense it can synthesize any arbitrary Boolean function. It is also a parity preserving gate in which the parity of input matches the parity of the output. This parity preserving gate allows any single fault to be detected at the circuit’s primary outputs. By using one PPPG a fault tolerant reversible full adder circuit can be realized. The proposed fault tolerant full adder (PFTFA) is used to design other arithmetic logic circuits for which it is used as the fundamental building block. The PFTFA gate is also used to implement high speed adders which are efficient basic building blocks of logic circuits. It has also been demonstrated that the proposed high speed adders are efficient in terms of gate count, garbage outputs and constant inputs than the existing counterparts.
KEYWORDS
Reversible logic, Garbage output, Reversible gate, Proposed Parity Preserving Gate, Constant inputs and Proposed fault tolerant full adder, Carry Skip Adder, Carry Look Ahead Adder, Ripple carry Adder
Original Source Link : http://aircconline.com/vlsics/V3N3/3312vlsics08.pdf
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