HIGH SPEED CONTINUOUS-TIME BANDPASS Σ∆ ADC FOR MIXED SIGNAL VLSI CHIPS
P.A.HarshaVardhini1 and Dr.M.MadhaviLatha2
1Ph.D Scholar, Dept. of ECE, J.N.T.U, Hyderabad, A.P, India.
2Professor and Head, Dept. of ECE, J.N.T.U, Hyderabad, A.P, India.
ABSTRACT
With the unremitting progress in VLSI technology, there is a commensurate increase in performance demand on analog to digital converter and are now being applied to wideband communication systems. sigma Delta (Σ∆) converter is a popular technique for obtaining high resolution with relatively small bandwidth. Σ∆ ADCs which trade sampling speed for resolution can benefit from the speed advantages of nm-CMOS technologies. This paper compares various Band pass sigma Delta ADC architectures, both continuous-time and discrete-time, in respect of power consumption and SNDR. Design of 2nd order multibit continuous time band pass Σ∆ modulator is discussed with the methods to resolve DAC non-idealities.
KEYWORDS
CMOS, Over sampling, Noise shaping, Sigma Delta Modulation, Bandpass Σ∆ modulator, Dynamic element matching, Data weighted averaging
Original Source Link : http://aircconline.com/vlsics/V3N2/3212vlsics06.pdf
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