Area, Delay and Power Comparison of Adder Topologies
R. Uma1,Vidya Vijayan2, M. Mohanapriya2 and Sharon Paul2,
1Pondicherry University, India and 2Rajiv Gandhi College of Engineering and Technology, India
Abstract
Adders form an almost obligatory component of every contemporary integrated circuit. The prerequisite of the adder is that it is primarily fast and secondarily efficient in terms of power consumption and chip area. This paper presents the pertinent choice for selecting the adder topology with the tradeoff between delay, power consumption and area. The adder topology used in this work are ripple carry adder, carry lookahead adder, carry skip adder, carry select adder, carry increment adder, carry save adder and carry bypass adder. The module functionality and performance issues like area, power dissipation and propagation delay are analyzed at 0.12µm 6metal layer CMOS technology using microwind tool.
Keywords :
Ripple Carry Adder, Carry Save Adder, Carry Increment Adder, Carry Select Adder.
Original Source Link : http://aircconline.com/vlsics/V3N1/3112vlsics13.pdf
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