BUS ENCODER FOR CROSSTALK AVOIDANCE IN RLC MODELED INTERCONNECTS

BUS ENCODER FOR CROSSTALK AVOIDANCE IN RLC MODELED INTERCONNECTS

G. Nagendra Babu1, Deepika Agarwal2, B. K. Kaushik3 and S. K. Manhas4

Department of Electronics and Computer Engineering, Indian Institute of Technology, Roorkee -247667, INDIA

ABSTRACT

Most of the encoding methods proposed in recent years have dealt with only RC modeled VLSI interconnects. For deep submicron technologies (DSM), on-chip inductive effects have increased due to faster clock speeds, smaller signal rise times and longer length of on-chip interconnects. All these issues raise the concern for crosstalk, propagation delay and power dissipation of overall. Therefore, this research work introduces an efficient Bus Encoder using Bus Inverting (BI) method. The proposed design dramatically reduces both crosstalk and power dissipation in RLC modeled interconnects which makes it suitable for current high-speed low-power VLSI interconnects. The proposed model demonstrates an overall reduction of power dissipation and crosstalk induced delay by 55.43% and 45.87%, respectively.

KEYWORDS

Inductance effects, Bus-invert, Crosstalk, Power dissipation. 

Original Source Link : http://aircconline.com/vlsics/V3N1/3112vlsics15.pdf

http://airccse.org/journal/vlsi/vol3.html