Performance Comparison of RF CMOS Low Noise Amplifiers in 0.18-µm technology scale

Performance Comparison of RF CMOS Low Noise Amplifiers in 0.18-µm technology scale

M.Sumathi*1, S.Malarvizhi 2 

*1 Research Scholar, Sathyabama University, Chennai -119,Tamilnadu 

2 HOD/ECE, SRM University, Kattankulathur – 603203, Kancheepuram District, Tamilnadu 

Abstract 

This paper presents the design theory of conventional single-ended LNA and differential LNA based on CMOS technology. The design concepts give an useful indication to the design trade-offs associated with NF, gain and impedance matching. Four LNA’s have been designed using technological design rules of TSMC 0.18-µm CMOS technology and this work mainly proposed for IEEE 802.11a applications. With 1.8V supply voltage, the proposed LNA’s achieve a gain higher than 19dB, a noise figure less than 4dB and impedance matching less than -10dB at 5GHz frequency. The goal of this paper is to highlight the efficient LNA architecture for achieving simultaneous gain, noise and input matching at low supply voltage. The performance of all LNA’s are analysed and compared using Agilent’s Advanced Design System Electronic  Design Automation tools.

Keywords: 

CMOS, Low Noise Amplifier (LNA), RF design, Wireless application. 

Original Source Link : http://aircconline.com/vlsics/V2N2/2211vlsics04.pdf

http://airccse.org/journal/vlsi/vol2.html