AREA-EFFICIENT DESIGN OF SCHEDULER FOR ROUTING NODE OF NETWORK-ON-CHIP
Rehan Maroofi,1 V. N. Nitnaware,2 and Dr. S. S. Limaye3
1Department of Electronics, Ramdeobaba Kamla Nehru College of Engg, Nagpur, India
2Department of EDT, Ramdeobaba Kamla Nehru College of Engg, Nagpur, India
3Jhulelal Institute of Technology, Nagpur, India
ABSTRACT
Traditional System-on-Chip (SoC) design employed shared buses for data transfer among various subsystems. As SoCs become more complex involving a larger number of subsystems, traditional busbased architecture is giving way to a new paradigm for on-chip communication. This paradigm is called Network-on-Chip (NoC). A communication network of point-to-point links and routing switches is used to facilitate communication between subsystems. The routing switch proposed in this paper consists of four components, namely the input ports, output ports, switching fabric, and scheduler. The scheduler design is described in this paper. The function of the scheduler is to arbitrate between requests by data packets for use of the switching fabric. The scheduler uses an improved round robin based arbitration algorithm. Due to the symmetric structure of the scheduler, an area-efficient design is proposed by folding the scheduler onto itself, thereby reducing its area roughly by 50%.
KEYWORDS
Network-on-Chip, System-on-Chip, On-chip routing switch, Scheduler, iSLIP, Synthesis.
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