Design of optimized Interval Arithmetic Multiplier
Rajashekar B.Shettar and Dr.R.M.Banakar
Department of Electronics and CommunicationBVB College of Engg and Technology, India
ABSTRACT
Many DSP and Control applications that require the user to know how various numerical errors(uncertainty) affect the result. This uncertainty is eliminated by replacing non-interval values with intervals. Since most DSPs operate in real time environments, fast processors are required to implement interval arithmetic. The goal is to develop a platform in which Interval Arithmetic operations are performed at the same computational speed as present day signal processors. So we have proposed the design and implementation of Interval Arithmetic multiplier, which operates with IEEE 754 numbers. The proposed unit consists of a floating point CSD multiplier, Interval operation selector. This architecture implements an algorithm which is faster than conventional algorithm of Interval multiplier . The cost overhead of the proposed unit is 30% with respect to a conventional floating point multiplier. The performance of proposed architecture is better than that of a conventional CSD floating-point multiplier, as it can perform both interval multiplication and floating-point multiplication as well as Interval comparisons
KEYWORDS
DSP, Floating-point, Interval arithmetic, comparator.
Original Source Link : http://aircconline.com/vlsics/V2N2/2211vlsics05.pdf
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