PERFORMANCE OF DIFFERENT CMOS LOGIC STYLES FOR LOW POWER AND HIGH SPEED

PERFORMANCE OF DIFFERENT CMOS LOGIC STYLES FOR LOW POWER AND HIGH SPEED 

Sreenivasa Rao.Ijjada, Ayyanna.G , G.Sekhar Reddy and Dr.V.Malleswara Rao

Department of ECE, GIT, GITAM University, Visakhapatnam, India

ABSTRACT

Designing high-speed low-power circuits with CMOS technology has been a major research problem for many years. Several logic families have been proposed and used to improve circuit performance beyond that of conventional static CMOS family. Fast circuit families are becoming attractive in deep submicron technologies since the performance benefits obtained from process scaling are decreasing as feature size decreases. This paper presents CMOS differential circuit families such as Dual rail domino logic and pseudo Nmos logic their delay and power variations in terms of adder design and logical design. Domino CMOS has become the prevailing logic family for high performance CMOS applications and it is extensively used in most state-of-the-art processors due to its high speed capabilities. The drawback of domino CMOS is that it provides only non-inverting functions because of its monotonic nature. Dual-Rail Domino logic, (also known as clocked Cascade voltage switch logic where both polarities of the output are generated, provides a robust solution to this problem.

KEYWORDS.

Static CMOS Logic, Dual rail domino logic, pseudo nmos, Low power.

Original Source Link : http://aircconline.com/vlsics/V2N2/2211vlsics06.pdf

http://airccse.org/journal/vlsi/vol2.html