A NEW APPROACH TO DESIGN LOW POWER CMOS FLASH A/D CONVERTER
Sudakar S. Chauhan1, S. Manabala2, S.C. Bose3 and R. Chandel4
1Department of Electronics & Communication Engineering, Graphic Era University, Dehradun, India
2,3Central Electronics Engineering Research Institute (CEERI), Pilani, India
4Department of Electronics & Communication Engineering, National Institute of Technology, Hamirpur, India
ABSTRACT
In the present paper, a 4-bit flash analog to digital converter for low power SoC application is presented. CMOS inverter has been used as a comparator and by adjusting the ratio of channel width and length, the switching threshold of the CMOS inverter is varied to detect the input analog signal. The simulation results show that this proposed 4-bit flash ADC consumes about 12.4 mW at 200M sample/s with 3.3V supply voltage in TSMC 0.35 µm process. Compared with the traditional flash ADC, this proposed method can reduce about 78% in power consumption.
KEYWORDS
CMOS Inverter, XOR gate based encoder, Flash ADC.
Original Source Link : http://aircconline.com/vlsics/V2N2/2211vlsics08.pdf
No comments:
Post a Comment