AREA OPTIMIZED FPGA IMPLEMENTATION FOR GENERATION OF RADAR PULSE COM-PRESSION SEQUENCES

AREA OPTIMIZED FPGA IMPLEMENTATION FOR GENERATION OF RADAR PULSE COM-PRESSION SEQUENCES

P. Tirumala rao1, P. Siva kumar2, Y.V. Apparao3, Y. Madhu babu4

1&2Dept. of ECE, Vignan institute of information technology, Vizag, Andhra Pradesh, India

3&4Dept. of ECE, GITAM University, Vizag, Andhra Pradesh, India

ABSTRACT

Pulse compression technique is most widely used in radar and communication areas. Its implementation requires an opti-mized and dedicated hardware. The real time implementation places several constraints such as area occupied, power con-sumption, etc. The good design needs optimization of these constraints. This paper concentrates on the design of optimized model which can reduce these. In the proposed architecture a single chip is used for generating the pulse compression se-quence like BPSk, QPSk, 6-PSK and other Polyphase codes. The VLSI architecture is implemented on the Field Programm-able Gate Array (FPGA) as it provides the flexibility of reconfigurability and reprogrammability .It was found that the proposed architecture has generated the pulse compression sequences efficiently while improving some of the parameters like area, power consumption and delay when compared to previous methods.

KEYWORDS

PULSE compression, Ternary sequence, Quaternary sequence, Polyphase sequence,Merit Factor, VLSI architecture, FPGA 

Original Source Link : http://aircconline.com/vlsics/V2N3/2311vlsics13.pdf

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