Design and test challenges in Nano-scale analog and mixed CMOS technology
Mouna Karmani, Chiraz Khedhiri and Belgacem Hamdi
Electronics & Microelectronics Laboratory, Monastir, Tunisia
Abstract
The continuous increase of integration densities in Complementary Metal–Oxide–Semiconductor (CMOS) technology has driven the rapid growth of very large scale integrated (VLSI) circuit for today's high-tech electronics industries from consumer products to telecommunications and computers. As CMOS technologies are scaled down into the nanometer range, analog and mixed integrated circuit (IC) design and testing have become a real challenge to ensure the functionality and quality of the product. The first part of the paper presents the CMOS technology scaling impact on design and reliability for consumer and critical applications. We then propose a discussion on the role and challenges of testing analog and mixed devices in the nano-scale era. Finally we present the IDDQ testing technique used to detect the most likely defects of bridging type occurring in analog CMOS circuits during the manufacturing process and creating a resistive path between VDD supply and the ground. To prove the efficiency of the proposed technique we design a CMOS 90nm operational amplifier (Opamp) and a Built in Current Sensor (BICS) to validate the technique and correlate it with post layout simulation results.
Keywords
Nano-CMOS technology, Analog testing, operational amplifier (Op amp), short (bridging) defect, resistive path, IDDQ Testing, BICS, 90nm technology
Original Source Link : http://aircconline.com/vlsics/V2N2/2211vlsics03.pdf
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