SURVEY ON POWER OPTIMIZATION TECHNIQUES FOR LOW POWER VLSI CIRCUIT IN DEEP SUBMICRON TECHNOLOGY

SURVEY ON POWER OPTIMIZATION TECHNIQUES FOR LOW POWER VLSI CIRCUIT IN DEEP SUBMICRON TECHNOLOGY

T. Suguna and M. Janaki Rani

Department of Electronics and Communication Engineering,

Dr.M.G. R Educational and Research Institute, Chennai, India

ABSTRACT

CMOS technology is the key element in the development of VLSI systems since it consumes less power. Power optimization has become an overridden concern in deep submicron CMOS technologies. Due to shrink in the size of device, reduction in power consumption and over all power management on the chip are the key challenges. For many designs power optimization is important in order to reduce package cost and to extend battery life. In power optimization leakage also plays a very important role because it has significant fraction in the total power dissipation of VLSI circuits. This paper aims to elaborate the developments and advancements in the area of power optimization of CMOS circuits in deep submicron region. This survey will be useful for the designer for selecting a suitable technique depending upon the requirement.

KEYWORDS

leakage power, low power, voltage scaling, power gating, transistor stacking, adiabatic logic. 

Original Source Link :http://aircconline.com/vlsics/V9N1/9118vlsi01.pdf

http://airccse.org/journal/vlsi/current.html