Design and Analysis of Multi Vt  and Variable Vt based Pipelined Adder for Low Power applications 

Shanthala S1, Cyril Prasanna Raj P2, Dr. S.Y.Kulkarni3

1 Research Scholar in EC Research Centre, NMAMIT, Nitte 

ABSTRACT

Majority of Digital Signal Processing (DSP) applications require arithmetic blocks such as multipliers and adders for hardware realization of complex algorithms. Power consumption of arithmetic blocks need to be minimized by use of low power techniques. In this paper, an experimental setup is developed to identify the sources of power dissipation and remedies that can be adopted to minimize power dissipation in arithmetic blocks. Use of low power techniques such as Multi Vt, variable Vt, pipelining, geometry scaling and use of appropriate load capacitance have been used to reduce power dissipation. A 4-bit pipelined adder is designed and the power dissipation is reduced to 4.17µW from 9.6µW. The designed pipelined adder can be used for DSP applications. 

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KEYWORDS

DSP, MAC, CMOS, Pipeline, Static and Dynamic

Original Source Link : http://aircconline.com/vlsics/V1N4/1210vlsics04.pdf

http://airccse.org/journal/vlsi/vol1.html