DESIGN APPROACH FOR FAULT TOLERANCE IN FPGA ARCHITECTURE
Ms. Shweta S. Meshram 1 and Ms. Ujwala A. Belorkar 2
1Department of electronics & telecommunication, Government College of Engineering & Technology, Amravati, India
2 Department of electronics & telecommunication, Hanuman Vyayam Prasarak Mandal’s College of Engineering & Technology, Amravati, India
Abstract
Failures of nano-metric technologies owing to defects and shrinking process tolerances give rise to significant challenges for IC testing. In recent years the application space of reconfigurable devices has grown to include many platforms with a strong need for fault tolerance. While these systems frequently contain hardware redundancy to allow for continued operation in the presence of operational faults, the need to recover faulty hardware and return it to full functionality quickly and efficiently is great. In addition to providing functional density, FPGAs provide a level of fault tolerance generally not found in mask-programmable devices by including the capability to reconfigure around operational faults in the field. Reliability and process variability are serious issues for FPGAs in the future. With advancement in process technology, the feature size is decreasing which leads to higher defect densities, more sophisticated techniques at increased costs are required to avoid defects. If nano-technology fabrication are applied the yield may go down to zero as avoiding defect during fabrication will not be a feasible option Hence, feature architecture have to be defect tolerant. In regular structure like FPGA, redundancy is commonly used for fault tolerance. In this work we present a solution in which configuration bit-stream of FPGA is modified by a hardware controller that is present on the chip itself. The technique uses redundant device for replacing faulty device and increases the yield.
Key Word
Fault tolerance, FPGA, hardware controller, redundancy.
Original Source Link : http://aircconline.com/vlsics/V2N1/2111vlsics08.pdf
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