SOFTWARE AND HARDWARE DESIGN CHALLENGES IN AUTOMOTIVE EMBEDDED SYSTEM

SOFTWARE AND HARDWARE DESIGN CHALLENGES IN AUTOMOTIVE EMBEDDED SYSTEM

Rajeshwari Hegde1, Geetishree Mishra1, K S Gurumurthy2

1BMS College of Engineering, Bangalore, India

2UVCE, Bangalore, India

ABSTRACT

Modern automotives integrate large amount of electronic devices to improve the driving safety and comfort. This growing number of Electronic Control Units (ECUs) with sophisticated software escalates the vehicle system design complexity. In this paper we explain the complexity of ECUs in terms of hardware and software and also we explore the possibility of Common Object Request Broker Architecture (CORBA) architecture for the integration of add-on software in ECUs. This reduces the complexity of the embedded system in vehicles and eases the ECU integration by reducing the total number of ECUs in the vehicles.

KEYWORDS

AUTOSAR, CORBA, ECU, OEM 

Original Source Link : http://aircconline.com/vlsics/V2N3/2311vlsics14.pdf

http://airccse.org/journal/vlsi/vol2.html

AREA OPTIMIZED FPGA IMPLEMENTATION FOR GENERATION OF RADAR PULSE COM-PRESSION SEQUENCES

AREA OPTIMIZED FPGA IMPLEMENTATION FOR GENERATION OF RADAR PULSE COM-PRESSION SEQUENCES

P. Tirumala rao1, P. Siva kumar2, Y.V. Apparao3, Y. Madhu babu4

1&2Dept. of ECE, Vignan institute of information technology, Vizag, Andhra Pradesh, India

3&4Dept. of ECE, GITAM University, Vizag, Andhra Pradesh, India

ABSTRACT

Pulse compression technique is most widely used in radar and communication areas. Its implementation requires an opti-mized and dedicated hardware. The real time implementation places several constraints such as area occupied, power con-sumption, etc. The good design needs optimization of these constraints. This paper concentrates on the design of optimized model which can reduce these. In the proposed architecture a single chip is used for generating the pulse compression se-quence like BPSk, QPSk, 6-PSK and other Polyphase codes. The VLSI architecture is implemented on the Field Programm-able Gate Array (FPGA) as it provides the flexibility of reconfigurability and reprogrammability .It was found that the proposed architecture has generated the pulse compression sequences efficiently while improving some of the parameters like area, power consumption and delay when compared to previous methods.

KEYWORDS

PULSE compression, Ternary sequence, Quaternary sequence, Polyphase sequence,Merit Factor, VLSI architecture, FPGA 

Original Source Link : http://aircconline.com/vlsics/V2N3/2311vlsics13.pdf

http://airccse.org/journal/vlsi/vol2.html

DESIGN OF A CMOS BANDGAP REFERENCE WITH LOWTEMPERATURE COEFFICIENT AND HIGH POWER SUPPLY REJECTION PERFORMANCE

DESIGN OF A CMOS BANDGAP REFERENCE WITH LOWTEMPERATURE COEFFICIENT AND HIGH POWER SUPPLY REJECTION PERFORMANCE 

Abhisek Dey1 and Tarun Kanti Bhattacharyya2

Department of Electronics & Electrical Communication Engineering, Indian Institute of Technology, Kharagpur, West Bengal, India 

ABSTRACT

A high precision temperature compensated CMOS bandgap reference is presented. The proposed circuit employs current-mode architecture that improves the temperature stability of the output reference voltage as well as the power supply rejection when compared to the conventional voltage-mode bandgap referenc. Using only first order compensation the new architecture can generate an output reference voltage of 550mV with a peak-to-peak variation of 400µV over a wide temperature range from -25oC to +100oC which corresponds to a temperature coefficient of 5.8ppm/oC. The output reference voltage exhibits a variation of 2.4mV for supply voltage ranging from 1.6V to 2.0V at typical process corner. A differential cascaded three-stage operational amplifier is included in the bandgap circuit to improve the power supply rejection of the BGR. Simulation result shows that the power supply rejection ratio of the proposed circuit is 79dB from DC up to 1kHz of frequency. The proposed bandgap reference is implemented using UMC 0.18µm CMOS process and it occupies an active layout area of 0.14mm2.

KEYWORDS

BGR, Temperature coefficient, PSRR. 

Original Source Link : http://aircconline.com/vlsics/V2N3/2311vlsics12.pdf

http://airccse.org/journal/vlsi/vol2.html

DESIGN AND IMPLEMENTATION OF FPGA BASED SIGNAL PROCESSING CARD

DESIGN AND IMPLEMENTATION OF FPGA BASED SIGNAL PROCESSING CARD

Priya Gupta1 and Deepak Gupta2

1Banasthali University, Rajasthan India

2Alpine System, New Delhi India

ABSTRACT

This paper describes the design of FPGA based signal processing card. An on board real time digital signal processing system is designed using FPGA. The platform can decode process of various kinds of digital and analog signals simultaneously. The design trend in this card is towards small size, high integration and fast real time processing. For the optimum performance a 16 bit 1 MSPS ADC is used which is interfaced with FPGA to make all the data processing onboard in real time. This card can be used in many signal processing based applications like audio signal processing, audio compression, digital image processing, video compression, speech processing, speech recognition, digital communications by interfacing several separate board using inbuilt I/O’s, each with a number of input channels that will communicate with each other in real time over a high speed communication link. The resulting images can be displayed directly on LCD or OLED panel displays using I/O’s peripherals. The project introduces many challenging issues, which are being addressed in turn with different prototype designs. These issues are the ADC performance, interfacing the ADCs to the FPGA, implementing the flexible processing  algorithms and high speed interconnection between the boards. 

Original Source Link : http://aircconline.com/vlsics/V2N3/2311vlsics11.pdf

http://airccse.org/journal/vlsi/vol2.html

Performance analysis of DWT based OFDM over FFT based OFDM and implementing on FPGA

Performance analysis of DWT based OFDM over FFT based OFDM and implementing on FPGA

Mrs. VEENA M.B1  & Dr. M.N.SHANMUKHA SWAMY2

1Research scholar, ECE Department, SJCE, Mysore, Karnataka, India

2Professor, ECE Department, SJCE, Mysore, Karnataka,India,

ABSTRACT

Growth in technology has led to unprecedented demand for high speed architectures for complex signal processing applications. In 4G wireless communication systems, bandwidth is a precious commodity, and service providers are continuously met with the challenge of accommodating more users with in a limited allocated bandwidth. To increase data rate of wireless medium with higher performance, OFDM (orthogonal frequency division multiplexing) is used. Recently DWT (Discrete wavelet transforms) is adopted in place of FFT (Fast Fourier transform) for frequency translation. Modulation schemes such as 16-QAM, 32-QAM, 64-QAM and 128-QAM (Quadrature amplitude modulation) have been used in the developed OFDM system for both DWT and FFT based model. In this paper we propose a DWT-IDWT based OFDM transmitter and receiver that achieve better performance in terms SNR and BER for AWGN channel. It proves all the wavelet families better over the IFFT-FFT implementation. The OFDM model is developed using Simulink, various test cases have been considered to verify its performance. The DWTOFDM using Lifting Scheme architecture is implemented on FPGA optimizing hardware, speed & cost. The wavelet filter used for this is Daubechies (9, 7) with N=2. The RTL code is written in Verilog-HDL and simulated in Modelsim. The design is then synthesized in Xilinx and implemented on Virtex5 FPGA board and the results were validated using ChipScope.

Keywords:

FFT, DWT, OFDM, BER, Lifting scheme, Simulink 

Original Source Link : http://aircconline.com/vlsics/V2N3/2311vlsics10.pdf

http://airccse.org/journal/vlsi/vol2.html

AREA-EFFICIENT DESIGN OF SCHEDULER FOR ROUTING NODE OF NETWORK-ON-CHIP

AREA-EFFICIENT DESIGN OF SCHEDULER FOR ROUTING NODE OF NETWORK-ON-CHIP

Rehan Maroofi,1 V. N. Nitnaware,2 and Dr. S. S. Limaye3

1Department of Electronics, Ramdeobaba Kamla Nehru College of Engg, Nagpur, India

2Department of EDT, Ramdeobaba Kamla Nehru College of Engg, Nagpur, India

3Jhulelal Institute of Technology, Nagpur, India

ABSTRACT

Traditional System-on-Chip (SoC) design employed shared buses for data transfer among various subsystems. As SoCs become more complex involving a larger number of subsystems, traditional busbased architecture is giving way to a new paradigm for on-chip communication. This paradigm is called Network-on-Chip (NoC). A communication network of point-to-point links and routing switches is used to facilitate communication between subsystems. The routing switch proposed in this paper consists of four components, namely the input ports, output ports, switching fabric, and scheduler. The scheduler design is described in this paper. The function of the scheduler is to arbitrate between requests by data packets for use of the switching fabric. The scheduler uses an improved round robin based arbitration algorithm. Due to the symmetric structure of the scheduler, an area-efficient design is proposed by folding the scheduler onto itself, thereby reducing its area roughly by 50%.

KEYWORDS

Network-on-Chip, System-on-Chip, On-chip routing switch, Scheduler, iSLIP, Synthesis. 

Original Source Link : http://aircconline.com/vlsics/V2N3/2311vlsics09.pdf

http://airccse.org/journal/vlsi/vol2.html

PIPELINED ARCHITECTURE OF 2D-DCT, QUANTIZATION AND ZIGZAG PROCESS FOR JPEG IMAGE COMPRESSION USING VHDL

PIPELINED ARCHITECTURE OF 2D-DCT, QUANTIZATION AND ZIGZAG PROCESS FOR JPEG IMAGE COMPRESSION USING VHDL

T.Pradeepthi1 and Addanki Purna Ramesh2

Department of ECE, Sri Vasavi Engg College, Tadepalligudem, West Godavari (dt), Andhra Pradesh, India

ABSTRACT

This paper presents the architecture and VHDL design of a Two Dimensional Discrete Cosine Transform (2D-DCT) with Quantization and zigzag arrangement. This architecture is used as the core and path in JPEG image compression hardware. The 2D- DCT calculation is made using the 2D- DCT Separability property, such that the whole architecture is divided into two 1D-DCT calculations by using a transpose buffer. Architecture for Quantization and zigzag process is also described in this paper. The quantization process is done using division operation. This design aimed to be implemented in Spartan-3E XC3S500 FPGA. The 2D- DCT architecture uses 1891 Slices, 51I/O pins, and 8 multipliers of one Xilinx Spartan-3E XC3S500E FPGA reaches an operating frequency of 101.35 MHz One input block with 8 x 8 elements of 8 bits each is processed in 6604 ns and pipeline latency is 140 clock cycles .

KEYWORDS

JPEG, discrete cosine transform (DCT), quantization, zigzag, FPGA 

Original Source Link : http://aircconline.com/vlsics/V2N3/2311vlsics08.pdf

http://airccse.org/journal/vlsi/vol2.html

SUB TEN MICRON CHANNEL DEVICES ACHIEVED BY VERTICAL ORGANIC THIN FILM TRANSISTOR

SUB TEN MICRON CHANNEL DEVICES ACHIEVED  BY VERTICAL ORGANIC THIN FILM TRANSISTOR

Abdul Rauf Khan1, S.S.K. Iyer2

1EC Department, Graphic Era University, Dehradun, Uttarakhand, INDIA,

2EE Department, IIT Kanpur, Kanpur, Uttar Pradesh, INDIA 

ABSTRACT

The channel lengths of the top contact organic thin film transistors are usually defined during their fabrication by optical lithography or by shadow masking during the metal deposition process. Realizing short channel (sub-ten micron channel length) transistors by lithography will require costly lithography equipment. On the other hand, it is extremely challenging to achieve short channel transistors using the low cost shadow mask process. One low cost method of achieving short channel devices is to build vertical transistors with the transistor, where the channel gets defined in the vertical part of the device. This paper shows that vertical channel top contact organic thin film  transistor has been successfullyrealized on the vertical edge of trench. This helped in creating the device with channel lengths less than ten microns, much smaller than what could be typically achieved with the use of shadow masks.

KEYWORDS

Organic Thin Film Transistors OTFT, Radio Frequency Identification RFID, Poly-thiophene PT, Thin film transistor TFT. 

Original Source Link : http://aircconline.com/vlsics/V2N3/2311vlsics07.pdf

http://airccse.org/journal/vlsi/vol2.html

POWER COMPARISON OF CMOS AND ADIABATIC FULL ADDER CIRCUITS

POWER COMPARISON OF CMOS AND ADIABATIC FULL ADDER CIRCUITS

Y. Sunil Gavaskar Reddy1 and V.V.G.S.Rajendra Prasad2

1Department of Electronics &Communication Engineering, Anurag Engineering College, JNTUniversity, Andhrapradesh,India

2Department of Electronics &Communication Engineering, Anurag Engineering College, JNTUniversity, Andhrapradesh,India

ABSTRACT

Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. Apart from the basic addition adders also used in performing useful operations such as subtraction, multiplication, division, address calculation, etc. In most of these systemsthe adder lies in the critical path that determines the overall performance of the system. In this paper conventional complementary metal oxide  emiconductor (CMOS) and adiabatic adder circuits are analyzed in terms of power and transistor count using 0.18UM technology.

KEYWORDS

Low-power, adiabatic logic, Full adder, CMOS, Pass transistor logic, Positive feed back adiabatic logic, Transmission gate logic, SERF adder

Original Source Link :http://aircconline.com/vlsics/V2N3/2311vlsics06.pdf

http://airccse.org/journal/vlsi/vol2.html

Events Classification in Log Audit

Events Classification in Log Audit 

Sabah Al-Fedaghi and Fahad Mahdi 

Computer Engineering Department, Kuwait University, Kuwait

ABSTRACT

Information security audit is a monitoring/logging mechanism to ensure compliance with regulations and to detect abnormalities, security breaches, and privacy violations; however, auditing too many events causes overwhelming use of system resources and impacts performance. Consequently, a classification of events is used to prioritize events and configure the log system. Rules can be applied according to this classification to make decisions about events to be archived and types of actions invoked by events. Current classification methodologies are fixed to specific types of incident occurrences and applied in terms of system-dependent description. In this paper, we propose a conceptual model that produces an implementation-independent logging scheme to monitor events.

KEYWORDS

Information security, event classification, audit system, log analysis. 

Original Source Link :http://airccse.org/journal/nsa/0410ijnsa5.pdf

http://airccse.org/journal/jnsa10_current.html

RELEVANCE OF GROOVED NMOSFETS IN ULTRA DEEP SUBMICRON REGION IN LOW POWER APPLICATIONS

RELEVANCE OF GROOVED NMOSFETS IN ULTRA DEEP SUBMICRON REGION IN LOW POWER APPLICATIONS

Subhra Dhar1, Manisha Pattanaik2, P. Rajaram3

1,2ABV-Indian Institute of Information Technology and Management, Gwalior Gwalior-474010, M.P., India

3Jiwaji University, Gwalior-474009, M.P., India

ABSTRACT

To manage the increasing static leakage in low power applications, solutions for leakage reduction are sought at the device design and process technology levels. In this paper, 90nm, 70nm and 50 nm groovedgate nMOS devices are simulated using Silvaco device simulator. By changing the corner angle and adjusting few structural parameters, static leakage reduction is achieved in grooved nMOSFETS in ultralow power applications. The simulation results show that leakage contributing currents like thesubthreshold current, punchthrough current and tunneling leakage current are reduced. The oxide thickness can be increased without increase in the gate induced drain leakage current, and ON-OFF current ratio is improved and maintained constant even in the deep submicron region. This study can be helpful for low power applications as the static leakage is reduced drastically, as well as be applicable to high speed devices as the ON current is maintained at a constant value. The results are compared with those of corresponding conventional planar devices to bring out the achievements of this work.

KEYWORDS

Planar MOSFET, Grooved MOSFET, Concave corner, Corner angle, Deep Submicron regime, DIBL

Original Source Link : http://aircconline.com/vlsics/V2N3/2311vlsics05.pdf

http://airccse.org/journal/vlsi/vol2.html

FPGA IMPLEMENTATION OF SOFT OUTPUT VITERBI ALGORITHM USING MEMORYLESS HYBRID REGISTER EXCHANGE METHOD

FPGA IMPLEMENTATION OF SOFT OUTPUT VITERBI ALGORITHM USING MEMORYLESS HYBRID REGISTER EXCHANGE METHOD

R .D. Kadam1 and S. L. Haridas2

1Department of Electronics and Telecomm. BDCE, Sevagram, RTM Nagpur University, India

2Department of Electronics and Telecomm. BDCE, Sevagram, RTM Nagpur University, India

ABSTRACT

The importance of convolutional codes is well established. They are widely used to encode digital data before transmission through noisy or error-prone communication channels to reduce occurrence of errors and memory. This paper presents novel decoding technique, memoryless Hybrid Register Exchange with simulation and FPGA implementation results. It requires single register as compared to Register Exchange Method (REM) & Hybrid Register Exchange Method (HREM); therefore the data trans-fer operations and ultimately the switching activity will get reduced.

KEYWORDS

Traceback method, Register Exchange Method, Hybrid Register Exchange Method, Memoryless HREM. 

Original Source Link : http://aircconline.com/vlsics/V2N3/2311vlsics04.pdf

http://airccse.org/journal/vlsi/vol2.html

A 80Ms/sec 10bit PIPELINED ADC Using 1.5Bit Stages And Built-in Digital Error Correction Logic

A 80Ms/sec 10bit PIPELINED ADC Using 1.5Bit Stages And Built-in Digital Error Correction Logic

P.Prasad Rao1 and Prof.K.Lal Kishore2

1Research Scholar, JNTU-Hyderabad, India

2Director, R&D, JNTU-Hyderabad, India

Abstract

 Use of pipelined ADCs is becoming increasingly popular both as stand alone parts and as embedded functional units in SOC design. They have acceptable resolution and high speed of operation and can be placed in relatively small area. The design is implemented in 0.18uM CMOS process. The design includes a folded cascode op-amp with a unity gain frequency of 200MHz at 88 deg. Phase margin and a dc gain of 75dB. The circuit employs a built in sample and hold circuit and a three phase non-overlapping clock.

Keywords

ADC, 1.5 bit stage, CMFB, Pipeline, Redundancy bit removal algorithm 

Original Source Link : http://aircconline.com/vlsics/V2N3/2311vlsics03.pdf

http://airccse.org/journal/vlsi/vol2.html

TEST GENERATION FOR ANALOG AND MIXED-SIGNAL CIRCUITS USING HYBRID SYSTEM MODELS

TEST GENERATION FOR ANALOG AND MIXED-SIGNAL CIRCUITS USING HYBRID SYSTEM MODELS

Tarik NAHHAL1 and Thao Dang2

1Department of Mathematics and Computer Science, Hassan II University, Casablanca,

2VERIMAG, 2 avenue de Vignate 32000 Gières, France 

ABSTRACT

In this paper we propose an approach for testing time-domain properties of analog and mixed-signal circuits. The approach is based on an adaptation of a recently developed test generation technique for hybrid systems and a new concept of coverage for such systems. The approach is illustrated by its application to some benchmark circuits. 

KEYWORDS

Hybrid System, Formal Methods in Conformance Testing, Analog and Mixed-Signal Circuit. 

Original Source Link : http://aircconline.com/vlsics/V2N3/2311vlsics02.pdf

http://airccse.org/journal/vlsi/vol2.html

A Fault Dictionary-Based Fault Diagnosis Approach for CMOS Analog Integrated Circuits

A Fault Dictionary-Based Fault Diagnosis Approach for CMOS Analog Integrated Circuits  

Mouna Karmani1, Chiraz Khedhiri1, Belgacem Hamdi1 & Brahim Bensalem2

1Electronics and Microelectronics Laboratory, Monastir, Tunisia

2Embedded and Communication Group, Intel Corporation, Chandler, AZ, USA 

Abstract:

In this paper, we propose a simulation-before-test (SBT) fault diagnosis methodology based on the use of a fault dictionary approach. This technique allows the detection and localization of the most likely defects of open-circuit type occurring in Complementary Metal–Oxide–Semiconductor (CMOS) analog integrated circuits (ICs) interconnects. The fault dictionary is built by simulating the most likely defects causing the faults to be detected at the layout level. Then, for each injected fault, the spectre’s frequency responses and the power consumption obtained by simulation are stored in a table which constitutes the fault dictionary. In fact, each line in the fault dictionary constitutes a fault signature used to identify and locate a considered defect. When testing, the circuit under test is excited with the same stimulus, and the responses obtained are compared to the stored ones. To prove the efficiency of the proposed technique, a full custom CMOS operational amplifier is implemented in 0.25 µm technology and the most likely faults of opencircuit type are deliberately injected and simulated at the layout level.

Keywords: 

Analog testing, fault diagnosis, fault dictionary, Fast Fourier Transform (FFT), power consumption, opencircuit fault. 

Original Source Link : http://aircconline.com/vlsics/V2N3/2311vlsics01.pdf

http://airccse.org/journal/vlsi/vol2.html

A BUS ENCODING TO REDUCE CROSSTALK NOISE EFFECT IN SYSTEM ON CHIP

A BUS ENCODING TO REDUCE CROSSTALK NOISE EFFECT IN SYSTEM ON CHIP

J.Venkateswara Rao1 and A.V.N.Tilak2

1Department of Electronics and Communication Engineering, Vignan Institute of Technology & Science, Deshmukhi, Nalgonda Dist. A.P, India.

21Department of Electronics and Communication Engineering, Gudlavalleru Engineering College Gudlavalleru, Krishna Dist. A.P, India.

ABSTRACT

This paper proposes a new bus coding scheme for reducing the crosstalk in System on chip(soc). As circuit geometries become smaller, wire interconnections become closer together and taller, thus increasing the cross-coupling capacitance between nets. At the same time, parasitic capacitance to the substrate becomes less as interconnections become narrower, and cell delays are reduced as transistors become smaller. With circuit geometries at 0.25 micron and above, substrate capacitance is usually the dominant effect. However, with geometries at 0.18 micron and below, the coupling capacitance between nets becomes significant, making crosstalk analysis increasingly important for accurate timing analysis. We show experimentally that the proposed codes allow reducing crosstalk delay by at least 14% based on available data.

KEYWORDS

Crosstalk, Encoding, SOC, parasitic, coupling Capacitance, micron, Forbidden Pattern free 

Original Source Link : http://aircconline.com/vlsics/V2N2/2211vlsics09.pdf

http://airccse.org/journal/vlsi/vol2.html

A NEW APPROACH TO DESIGN LOW POWER CMOS FLASH A/D CONVERTER

A NEW APPROACH TO DESIGN LOW POWER CMOS FLASH A/D CONVERTER

Sudakar S. Chauhan1, S. Manabala2, S.C. Bose3 and R. Chandel4

1Department of Electronics & Communication Engineering, Graphic Era University, Dehradun, India

2,3Central Electronics Engineering Research Institute (CEERI), Pilani, India

4Department of Electronics & Communication Engineering, National Institute of Technology, Hamirpur, India

ABSTRACT

In the present paper, a 4-bit flash analog to digital converter for low power SoC application is presented. CMOS inverter has been used as a comparator and by adjusting the ratio of channel width and length, the switching threshold of the CMOS inverter is varied to detect the input analog signal. The simulation results show that this proposed 4-bit flash ADC consumes about 12.4 mW at 200M sample/s with 3.3V supply voltage in TSMC 0.35 µm process. Compared with the traditional flash ADC, this proposed method can reduce about 78% in power consumption.

KEYWORDS

CMOS Inverter, XOR gate based encoder, Flash ADC. 

Original Source Link : http://aircconline.com/vlsics/V2N2/2211vlsics08.pdf

http://airccse.org/journal/vlsi/vol2.html

NEW DESIGN METHODOLOGIES FOR HIGH-SPEED MIXED-MODE CMOS FULL ADDER CIRCUITS

NEW DESIGN METHODOLOGIES FOR HIGH-SPEED MIXED-MODE CMOS FULL ADDER CIRCUITS

Subodh Wairya, Rajendra Kumar Nagaria and Sudarshan Tiwari

Department of Electronics & Communication Engineering,M.N.N.I.T, Allahabad, India

ABSTRACT

This paper presents the design of high-speed full adder circuits using a new CMOS mixed mode logic family. The objective of this work is to present a new full adder design circuits combined with current mode circuit in one unit to implement a full adder cell. This paper also discusses a high- speed hybrid majority function based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure with conventional static and dynamic CMOS logic circuit. The static Majority function (bridge) design style enjoys a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as lower power consumption by using bridge transistors. This technique helps in reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of mixedmode logic designs. Dynamic CMOS circuits enjoy area, delay and testability advantages over static CMOS circuits. Simulation results illustrate the superiority of the new designed adder circuits against the reported conventional CMOS, dynamic and majority function adder circuits, in terms of power, delay, power delay product (PDP) and energy delay product (EDP). The design is implemented on UMC 0.18µm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and simulations are carried out on Spectre S.

KEYWORDS

Full adder, Majority-Not gate, Dynamic circuits, MOSCAP, Power-delay product (PDP), Very Large Scale Integrated (VLSI) Circuits, Current mode logic, Hybrid XOR-XNOR circuit, Bridge full adder. 

Original Source Link : http://aircconline.com/vlsics/V2N2/2211vlsics07.pdf

http://airccse.org/journal/vlsi/vol2.html

PERFORMANCE OF DIFFERENT CMOS LOGIC STYLES FOR LOW POWER AND HIGH SPEED

PERFORMANCE OF DIFFERENT CMOS LOGIC STYLES FOR LOW POWER AND HIGH SPEED 

Sreenivasa Rao.Ijjada, Ayyanna.G , G.Sekhar Reddy and Dr.V.Malleswara Rao

Department of ECE, GIT, GITAM University, Visakhapatnam, India

ABSTRACT

Designing high-speed low-power circuits with CMOS technology has been a major research problem for many years. Several logic families have been proposed and used to improve circuit performance beyond that of conventional static CMOS family. Fast circuit families are becoming attractive in deep submicron technologies since the performance benefits obtained from process scaling are decreasing as feature size decreases. This paper presents CMOS differential circuit families such as Dual rail domino logic and pseudo Nmos logic their delay and power variations in terms of adder design and logical design. Domino CMOS has become the prevailing logic family for high performance CMOS applications and it is extensively used in most state-of-the-art processors due to its high speed capabilities. The drawback of domino CMOS is that it provides only non-inverting functions because of its monotonic nature. Dual-Rail Domino logic, (also known as clocked Cascade voltage switch logic where both polarities of the output are generated, provides a robust solution to this problem.

KEYWORDS.

Static CMOS Logic, Dual rail domino logic, pseudo nmos, Low power.

Original Source Link : http://aircconline.com/vlsics/V2N2/2211vlsics06.pdf

http://airccse.org/journal/vlsi/vol2.html

Design of optimized Interval Arithmetic Multiplier

Design of optimized Interval Arithmetic Multiplier

Rajashekar B.Shettar and Dr.R.M.Banakar

Department of Electronics and CommunicationBVB College of Engg and Technology, India

ABSTRACT

Many DSP and Control applications that require the user to know how various numerical errors(uncertainty) affect the result. This uncertainty is eliminated by replacing non-interval values with intervals. Since most DSPs operate in real time environments, fast processors are required to implement interval arithmetic. The goal is to develop a platform in which Interval Arithmetic operations are performed at the same computational speed as present day signal processors. So we have proposed the design and implementation of Interval Arithmetic multiplier, which operates with IEEE 754 numbers. The proposed unit consists of a floating point CSD multiplier, Interval operation selector. This architecture implements an algorithm which is faster than conventional algorithm of Interval multiplier . The cost overhead of the proposed unit is 30% with respect to a conventional floating point multiplier. The performance of proposed architecture is better than that of a conventional CSD floating-point multiplier, as it can perform both interval multiplication and floating-point multiplication as well as Interval comparisons

KEYWORDS

 DSP, Floating-point, Interval arithmetic, comparator. 

Original Source Link : http://aircconline.com/vlsics/V2N2/2211vlsics05.pdf

http://airccse.org/journal/vlsi/vol2.html

Performance Comparison of RF CMOS Low Noise Amplifiers in 0.18-µm technology scale

Performance Comparison of RF CMOS Low Noise Amplifiers in 0.18-µm technology scale

M.Sumathi*1, S.Malarvizhi 2 

*1 Research Scholar, Sathyabama University, Chennai -119,Tamilnadu 

2 HOD/ECE, SRM University, Kattankulathur – 603203, Kancheepuram District, Tamilnadu 

Abstract 

This paper presents the design theory of conventional single-ended LNA and differential LNA based on CMOS technology. The design concepts give an useful indication to the design trade-offs associated with NF, gain and impedance matching. Four LNA’s have been designed using technological design rules of TSMC 0.18-µm CMOS technology and this work mainly proposed for IEEE 802.11a applications. With 1.8V supply voltage, the proposed LNA’s achieve a gain higher than 19dB, a noise figure less than 4dB and impedance matching less than -10dB at 5GHz frequency. The goal of this paper is to highlight the efficient LNA architecture for achieving simultaneous gain, noise and input matching at low supply voltage. The performance of all LNA’s are analysed and compared using Agilent’s Advanced Design System Electronic  Design Automation tools.

Keywords: 

CMOS, Low Noise Amplifier (LNA), RF design, Wireless application. 

Original Source Link : http://aircconline.com/vlsics/V2N2/2211vlsics04.pdf

http://airccse.org/journal/vlsi/vol2.html