REDUCTION OF BUS TRANSITION FOR COMPRESSED CODE SYSTEMS
S. R. Malathi, R. Ramya Asmi
Department of Computer Science and Engineering, Sri Venkateswara College of Engineering, Chennai, India
ABSTRACT
Low power VLSI circuit design is one of the most important issues in present day technology. One of the ways of reducing power is to reduce the number of transitions on the bus. The main focus here is to present a method for reducing the power consumption of compressed-code systems by inverting the bits that are transmitted on the bus. Compression will generally increase bit-toggling, as it removes redundancies from the code transmitted on the bus. Arithmetic coding technique is used for compression /decompression and bit-toggling reduction is done by using shift invert coding technique. Therefore, there is also an additional challenge, to find the right balance between compression ratio and the bit-toggling reduction. This technique requires only 2 extra bits for the low Power coding, irrespective of the bit-width of the bus for compressed data.
KEYWORDS
Low power VLSI, Bus transition reduction, Arithmetic coding, Compressed Code systems.
Original Source Link : http://aircconline.com/vlsics/V4N1/4113vlsics10.pdf
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