A STUDY OF ENERGY-AREA TRADEOFFS OF VARIOUS ARCHITECTURAL STYLES FOR ROUTING INPUTS IN A DOMAIN SPECIFIC RECONFIGURABLE FABRIC
Anil Yadav1, Justin Stander2, Alex K. Jones2, and Gayatri Mehta1
1Department of Electrical Engineering, University of North Texas, Denton, TX, USA
2Department of Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh, PA, USA
ABSTRACT
Coarse-grained reconfigurable fabrics (CGRF’s) have great promise for achieving low-energy flexible designs for an application domain. However a universally accepted architecture for coarse-grained reconfigurable fabrics has not yet crystallized, and many architectural options are still un- der consideration by the research and industry community. One scientific question is how to efficiently route inputs through a CGRF. This paper addresses this question in part by exploring various alternative input solu- tions for a stripe-based fabric. Alternative architectural styles examined in this paper include (i) integrated constants (IC) approach where constants are loaded in the registers local to the functional units; (ii) inputs coming from the side (ICS) where both constants and variable inputs can be routed to the stripe directly where needed; (iii) ICS with extended vertical interconnect (ICS-EV); and (iv) a combination of dedicated pass gates (DPs) with standard, IC, ICS, and ICS-EV architecture styles. We implemented these architecture styles using 90 nm ASIC process from Synopsys. We perform a detailed area and energy analysis on these architectures and present quantitative results in this paper. We observed that the fabric with ICS and 50% DPs is the best among these options, providing 31% energy savings and 62% area savings over a baseline architecture for our benchmark set.
KEYWORDS
Reconfigurable computing, domain-specific architecture, reconfigurable architecture, coarse-grained fabric
Original Sorce Link : http://aircconline.com/vlsics/V4N1/4113vlsics07.pdf
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