IMPLEMENTATION OF COMPACTION ALGORITHM FOR ATPG GENERATED PARTIALLY SPECIFIED TEST DATA
Vaishali Dhare1 and Dr. Usha Mehta2
1Assistant Professor, Institute of Technology, Nirma University, Ahmedabad
2Senior Associate Professor, Institute of Technology, Nirma University, Ahmedabad
ABSTRACT :
In this paper the ATPG is implemented using C++. This ATPG is based on fault equivalence concept in which the number of faults gets reduced before compaction method. This ATPG uses the line justification and error propagation to find the test vectors for reduced fault set with the aid of controllability and observability. Single stuck at fault model is considered. The programs are developed for fault equivalence method, controllability Observability, automatic test pattern generation and test data compaction using object oriented language C++. ISCAS 85 C17 circuit was used for analysis purpose along with other circuits. Standard ISCAS (International Symposium on Circuits And Systems) netlist format was used. The flow charts and results for ISCAS 85 C17 circuits along with other netlists are given in this paper. The test vectors generated by the ATPG further compacted to reduce the test vector data. The algorithm is developed for the test vector compaction and discussed along with results.
KEYWORDS :
Test vector, compaction, ISCAS, ATPG.
Original Source Link : http://aircconline.com/vlsics/V4N1/4113vlsics08.pdf
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