REALIZATION OF TRANSMITTER AND RECEIVER ARCHITECTURE FOR DOWNLINK CHANNELS IN 3-GPP LTE
S. Syed Ameer Abbas#1a, J. Rahumath Nisha#1 ,M. Beril Sahaya Mary#1,S. J. Thiruvengadam#2b
aAssistant Professor, b Professor #Department of Electronics and Communication Engineering
1Mepco Schlenk Engineering College, Sivakasi- 626005, India
2Thiagarajar College of Engineering, Madurai- 625015, India
ABSTRACT
Long Term Evolution (LTE), the next generation of radio technologies designed to increase the capacity and speed of mobile networks. The future communication systems require much higher peak rate for the air interface but very short processing delay. This paper mainly focuses on to improve the processing speed and capability and decrease the processing delay of the downlink channels using the parallel processing technique. This paper proposes Parallel Processing Architecture for both transmitter and receiver for Downlink channels in 3GPP-LTE. The Processing steps include Scrambling, Modulation, Layer mapping, Precoding and Mapping to the REs in transmitter side. Similarly demapping from the REs, Decoding and Detection, Delayer mapping and Descrambling in Receiver side. Simulation is performed by using modelsim and Implementation is achieved using Plan Ahead tool and virtex 5 FPGA.Implemented results are discussed in terms of RTL design, FPGA editor, power estimation and resource estimation.
KEYWORDS
PBCH, PMCH, PDCCH, PDSCH, PCFICH, OFDM, MBSFN, MBMS
Original Source Link : http://aircconline.com/vlsics/V4N1/4113vlsics02.pdf
http://airccse.org/journal/vlsi/vol4.html
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