A NOVEL POWER REDUCTION TECHNIQUE FOR DUAL-THRESHOLD DOMINO LOGIC IN SUB-65NM TECHNOLOGY

A NOVEL POWER REDUCTION TECHNIQUE FOR DUAL-THRESHOLD DOMINO LOGIC IN SUB-65NM TECHNOLOGY

Tarun Kr. Gupta1 and Kavita Khare2

Department of Electronics and Communication Engineering, MANIT, Bhopal, India

ABSTRACT

A novel technique for dual- threshold is proposed and examined with inputs and clock signals combinationin 65nm dual- threshold footerless domino circuit for reduced leakage current. In this technique a p-type and an n-type leakage controlled transistor (LCTs) are introduced between the pull-up and pull-down network and the gate of one is controlled by the source of the other. A high-threshold transistor is used in the input for reducing gate oxide leakage current which becomes dominant in nanometer technology. Simulations based on 65nm BISM4 model for proposed domino circuits shows that CLIL (clock low and input low) and CHIH (clock high and input high) state is ineffective for lowering leakage current. The CLIH (clock low input high) state is only effective to suppress the leakage at low and high temperatures for wide fan-in domino circuits but for AND gate CHIL (clock high input low) state is preferred to reduce the leakage current. The proposed circuit technique for AND2, OR2, OR4 and OR8 circuits reduces the active power consumption by 39.6% to 57.9% and by 32.4% to 40.3% at low and high die temperatures respectively when compared to the standard dual-threshold voltage domino logic circuits.

KEYWORDS

Dual-Threshold, Domino logic, Subthreshold leakage, Gate oxide tunneling, Leakage current.

Original Source Link : http://aircconline.com/vlsics/V4N1/4113vlsics04.pdf

http://airccse.org/journal/vlsi/vol4.html