FGMOS BASED LOW-VOLTAGE LOW-POWER HIGH OUTPUT IMPEDANCE REGULATED CASCODE CURRENT MIRROR

FGMOS BASED LOW-VOLTAGE LOW-POWER HIGH OUTPUT IMPEDANCE REGULATED CASCODE CURRENT MIRROR

Abhinav Anand, Prof. Sushanta K. Mandal, Anindita Dash3, B. Shivalal Patro

School of Electronics Engineering, KIIT University, Bhubaneswar, India

ABSTRACT

Floating Gate MOS (FGMOS) transistors can be very well implemented in lieu of conventional MOSFET for design of a low-voltage, low-power current mirror. Incredible features of flexibility, controllability and tunability of FGMOS yields better results with respect to power, supply voltage and output swing. This paper presents a new current mirror designed with FGMOS which exhibit high output impedance, higher current range, very low power dissipation and higher matching accuracy. It achieves current range of up to 1500 µA, high output impedance of 1.125 TΩ, bandwidth of 4.1 MHz and dissipates power as low as 10.56 µW. The proposed design has been simulated using Cadence Design Environment in 180 nm CMOS process technology with +1.0 Volt single power supply.

KEYWORDS

Floating Gate MOSFET, Current Mirror, Regulated Cascode, Low-Voltage & Low-Power 

Original Source Link : http://aircconline.com/vlsics/V4N2/4213vlsics04.pdf

http://airccse.org/journal/vlsi/vol4.html

ESTABLISHING A MOLECULAR COMMUNICATION CHANNEL FOR NANO NETWORKS

ESTABLISHING A MOLECULAR COMMUNICATION CHANNEL FOR NANO NETWORKS

Prachi Raut1 and Nisha Sarwade2

1Department of Electrical Engineering, VJTI, Mumbai, India

2Department of Electrical Engineering, VJTI, Mumbai, India

ABSTRACT

Nano machines can be connected together in a nano network. Molecular communication provides the most practical way in which nano machines can communicate with each other. This paper presents a review of pioneering research work in mathematical modelling and channel characterization of molecular communication for nano networks. It is reported that propagation of molecules can be modelled as deterministic as well as stochastic processes. Channel performance metrics like channel capacity, mutual information, gain/delay etc. have been estimated by various research groups. However, these parameters must be validated by evaluation of physical systems. Certain challenging issues like Brownian motion with negative drift, synchronization and inter-symbol interference in molecular channel are still open for investigation. Functionalities of higher network layers like modulation, error correction, routing etc. are yet to be exploited.

KEYWORDS

Nano Networks, Molecular Communication, Diffusion channel, Channel capacity 

Original Source Link : http://aircconline.com/vlsics/V4N2/4213vlsics03.pdf

http://airccse.org/journal/vlsi/vol4.html

EVALUATION OF OPTICALLY ILLUMINATED MOSFET CHARACTERISTICS BY TCAD SIMULATION

EVALUATION OF OPTICALLY ILLUMINATED MOSFET CHARACTERISTICS BY TCAD SIMULATION

Prerana Jain1 and Mishra B.K2

1SKVM’s NMIMS,Vile Parle(W),Mumbai,India

2Principal, Thakur College of Engg and Technology, Mumbai

ABSTRACT

In this paper we report effect of optical illumination on Silicon MOSFET. The MOSFET has been studied in respect of current voltage, transconductance admittance and scattering parameters. Gain analysis of the Silicon MOSFET is done in dark and under optical illumination. The device is fabricated using ATHENA™ process simulator and the device simulation is performed using ATLAS™ from SILVACO international. The simulation results indicate potential of MOSFET as optically sensitive structure which can be used for increase in data transmission/reception rates, reduction of interconnect delays, elimination of clock skew, or as a photodetector for optoelectronic applications at low and radio frequency.

KEYWORDS

AC, DC, MOSFET, Optical Illumination, RF, Simulation. 

Original Source Link : http://aircconline.com/vlsics/V4N2/4213vlsics02.pdf

http://airccse.org/journal/vlsi/vol4.html

AN INVESTIGATION INTO THE RELATIONSHIPS BETWEEN LOGICAL OPERATIONS

AN INVESTIGATION INTO THE RELATIONSHIPS BETWEEN LOGICAL OPERATIONS

Maher A. Nabulsi1 and Ahmad Abusukhon2

1Department of Computer Science, Al-Zaytoonah Private University, Amman, Jordan

2Department of Computer Network, Al-Zaytoonah Private University, Amman, Jordan

ABSTRACT

Boolean algebra (logical operations) is the backbone of computer software and hardware systems. Investigating new relationships between logical operations may help designing new computer algorithms. In this paper we propose to investigate the inverse relationships between the Exclusive-OR and Equivalence functions for three, four and five- variable functions. In addition, we propose to investigate the inverse relationships between the Inhibition and Implication functions for three and four-variable functions.

KEYWORDS

Exclusive -OR, Equivalence, Implication, Inhibition, Inverse. 

Original Source Link : http://aircconline.com/vlsics/V4N2/4213vlsics01.pdf

http://airccse.org/journal/vlsi/vol4.html

REDUCTION OF BUS TRANSITION FOR COMPRESSED CODE SYSTEMS

REDUCTION OF BUS TRANSITION FOR COMPRESSED CODE SYSTEMS

S. R. Malathi, R. Ramya Asmi

Department of Computer Science and Engineering, Sri Venkateswara College of Engineering, Chennai, India

ABSTRACT

Low power VLSI circuit design is one of the most important issues in present day technology. One of the ways of reducing power is to reduce the number of transitions on the bus. The main focus here is to present a method for reducing the power consumption of compressed-code systems by inverting the bits that are transmitted on the bus. Compression will generally increase bit-toggling, as it removes redundancies from the code transmitted on the bus. Arithmetic coding technique is used for compression /decompression and bit-toggling reduction is done by using shift invert coding technique. Therefore, there is also an additional challenge, to find the right balance between compression ratio and the bit-toggling reduction. This technique requires only 2 extra bits for the low Power coding, irrespective of the bit-width of the bus for compressed data.

KEYWORDS

Low power VLSI, Bus transition reduction, Arithmetic coding, Compressed Code systems. 

Original Source Link : http://aircconline.com/vlsics/V4N1/4113vlsics10.pdf

http://airccse.org/journal/vlsi/vol4.html

A MULTI-OBJECTIVE PERSPECTIVE FOR OPERATOR SCHEDULING USING FINEGRAINED DVS ARCHITECTURES

A MULTI-OBJECTIVE PERSPECTIVE FOR OPERATOR SCHEDULING USING FINEGRAINED DVS ARCHITECTURES

Rajdeep Mukherjee, Priyankar Ghosh, Pallab Dasgupta and Ajit Pal

Department of Computer Science and Engineering Indian Institute of Technology Kharagpur

ABSTRACT :

The stringent power budget of fine grained power managed digital integrated circuits have driven chip designers to optimize power at the cost of area and delay, which were the traditional cost criteria for circuit optimization. The emerging scenario motivates us to revisit the classical operator scheduling problem under the availability of DVFS enabled functional units that can trade-off cycles with power. We study the design space defined due to this trade-off and present a branch-and-bound(B/B) algorithm to explore this state space and report the pareto-optimal front with respect to area and power. The scheduling also aims at maximum resource sharing and is able to attain sufficient area and power gains for complex benchmarks when timing constraints are relaxed by sufficient amount. Experimental results show that the algorithm that operates without any user constraint(area/power) is able to solve the problem for mostavailable benchmarks, and the use of power budget or area budget constraints leads to significant performance gain.

KEYWORDS:

Scheduling, Pareto-optimal, Fine-grained DVS, Branch-and- Bound

Original Source Link : http://aircconline.com/vlsics/V4N1/4113vlsics09.pdf

http://airccse.org/journal/vlsi/vol4.html

Efficient Absolute Difference Circuit for SAD Computation On FPGA

IMPLEMENTATION OF COMPACTION ALGORITHM FOR ATPG GENERATED PARTIALLY SPECIFIED TEST DATA

IMPLEMENTATION OF COMPACTION ALGORITHM FOR ATPG GENERATED PARTIALLY SPECIFIED TEST DATA

Vaishali Dhare1 and Dr. Usha Mehta2

1Assistant Professor, Institute of Technology, Nirma University, Ahmedabad

2Senior Associate Professor, Institute of Technology, Nirma University, Ahmedabad

ABSTRACT :

In this paper the ATPG is implemented using C++. This ATPG is based on fault equivalence concept in which the number of faults gets reduced before compaction method. This ATPG uses the line justification and error propagation to find the test vectors for reduced fault set with the aid of controllability and observability. Single stuck at fault model is considered. The programs are developed for fault equivalence method, controllability Observability, automatic test pattern generation and test data compaction using object oriented language C++. ISCAS 85 C17 circuit was used for analysis purpose along with other circuits. Standard ISCAS (International Symposium on Circuits And Systems) netlist format was used. The flow charts and results for ISCAS 85 C17 circuits along with other netlists are given in this paper. The test vectors generated by the ATPG further compacted to reduce the test vector data. The algorithm is developed for the test vector compaction and discussed along with results. 

KEYWORDS :

Test vector, compaction, ISCAS, ATPG. 

Original Source Link : http://aircconline.com/vlsics/V4N1/4113vlsics08.pdf

http://airccse.org/journal/vlsi/vol4.html

A STUDY OF ENERGY-AREA TRADEOFFS OF VARIOUS ARCHITECTURAL STYLES FOR ROUTING INPUTS IN A DOMAIN SPECIFIC RECONFIGURABLE FABRIC

A STUDY OF ENERGY-AREA TRADEOFFS OF VARIOUS ARCHITECTURAL STYLES FOR ROUTING INPUTS IN A DOMAIN SPECIFIC RECONFIGURABLE FABRIC

Anil Yadav1, Justin Stander2, Alex K. Jones2, and Gayatri Mehta1

1Department of Electrical Engineering, University of North Texas, Denton, TX, USA

2Department of Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh, PA, USA

ABSTRACT

Coarse-grained reconfigurable fabrics (CGRF’s) have great promise for achieving low-energy flexible designs for an application domain. However a universally accepted architecture for coarse-grained reconfigurable fabrics has not yet crystallized, and many architectural options are still un- der consideration by the research and industry community. One scientific question is how to efficiently route inputs through a CGRF. This paper addresses this question in part by exploring various alternative input solu- tions for a stripe-based fabric. Alternative architectural styles examined in this paper include (i) integrated constants (IC) approach where constants are loaded in the registers local to the functional units; (ii) inputs coming from the side (ICS) where both constants and variable inputs can be routed to the stripe directly where needed; (iii) ICS with extended vertical interconnect (ICS-EV); and (iv) a combination of dedicated pass gates (DPs) with standard, IC, ICS, and ICS-EV architecture styles. We implemented these architecture styles using 90 nm ASIC process from Synopsys. We perform a detailed area and energy analysis on these architectures and present quantitative results in this paper. We observed that the fabric with ICS and 50% DPs is the best among these options, providing 31% energy savings and 62% area savings over a baseline architecture for our benchmark set. 

KEYWORDS

Reconfigurable computing, domain-specific architecture, reconfigurable architecture, coarse-grained fabric 

Original Sorce Link : http://aircconline.com/vlsics/V4N1/4113vlsics07.pdf

http://airccse.org/journal/vlsi/vol4.html

TERNARY TREE ASYNCHRONOUS INTERCONNECT NETWORK FOR GALS’ SOC

TERNARY TREE ASYNCHRONOUS INTERCONNECT NETWORK FOR GALS’ SOC

Vivek E. Khetade1, Dr. S. S. Limaye2

1Department of Electronic Design Technology Shri Ramdeobaba College of Engineering & Management, Rashtrasant Tukdoji Maharaj Nagpur university Nagpur, India

2Department of electronics engineering,Jhulelal Institute of Technology Rashtrasant Tukdoji Maharaj Nagpur university Nagpur, India

ABSTRACT

Interconnect fabric requires easy integration of computational block operating with unrelated clocks. This paper presents asynchronous interconnect with ternary tree asynchronous network for Globally Asynchronous Locally Synchronous (GALS) system-on-chip (SOC). Here architecture is proposed for interconnection with ternary tree asynchronous network where ratio of number NOC design unit and number of router is 4:1,6:2, 8:3,10:4 etc .It is scalable for any number of NOC design unit. It offers an easy integration of different clock domain with low communication overhead .NOC design unit for GALS ‘SOC is formulated by wrapping synchronous module with input port along with input port controller, output port along with output port controller and local clock generator. It creates the interface between synchronous to asynchronous and asynchronous to synchronous. For this purpose four port asynchronous routers is designed with routing element and output arbitration and buffering with micro-pipeline. This interconnect fabric minimizes silicon area, minimize Latency and maximize throughput. Here functional model is made for TTAN and application MPEG4 is mapped on the Network .Desired traffic pattern is generated and performance of the network is evaluated. Significant improvement in the network performance parameter has been observed. 

KEYWORDS

GALS, NOC, asynchronous design, ternary tree network, data synchronization

Original Source Link : http://aircconline.com/vlsics/V4N1/4113vlsics06.pdf

http://airccse.org/journal/vlsi/vol4.html

DUAL FIELD DUAL CORE SECURE CRYPTOPROCESSOR ON FPGA PLATFORM

DUAL FIELD DUAL CORE SECURE CRYPTOPROCESSOR ON FPGA PLATFORM

C Veeraraghavan1  and K Rajendran2

1Department of Electronics and communication, Sri Krishna Arts and Science College, Coimbatore,Tamilnadu, India

2Department of Electronics, Government Arts College for women, Ramanathapuram, Tamilnadu, India

ABSTRACT

This paper is devoted to the design of dual core crypto processor for executing both Prime field and binary field instructions. The proposed design is specifically optimized for Field programmable gate array (FPGA) platform. Combination of two different field (prime field GF(p) and Binary field GF(2m)) instructions execution is analysed.The design is implemented in Spartan 3E and virtex5. Both the performance results are compared. The implementation result shows the execution of parallelism using dual field instructions

KEYWORDS

Crypto processor, FPGA, Prime field, Binary field.

Original Source Link : http://aircconline.com/vlsics/V4N1/4113vlsics05.pdf

http://airccse.org/journal/vlsi/vol4.html

A NOVEL POWER REDUCTION TECHNIQUE FOR DUAL-THRESHOLD DOMINO LOGIC IN SUB-65NM TECHNOLOGY

A NOVEL POWER REDUCTION TECHNIQUE FOR DUAL-THRESHOLD DOMINO LOGIC IN SUB-65NM TECHNOLOGY

Tarun Kr. Gupta1 and Kavita Khare2

Department of Electronics and Communication Engineering, MANIT, Bhopal, India

ABSTRACT

A novel technique for dual- threshold is proposed and examined with inputs and clock signals combinationin 65nm dual- threshold footerless domino circuit for reduced leakage current. In this technique a p-type and an n-type leakage controlled transistor (LCTs) are introduced between the pull-up and pull-down network and the gate of one is controlled by the source of the other. A high-threshold transistor is used in the input for reducing gate oxide leakage current which becomes dominant in nanometer technology. Simulations based on 65nm BISM4 model for proposed domino circuits shows that CLIL (clock low and input low) and CHIH (clock high and input high) state is ineffective for lowering leakage current. The CLIH (clock low input high) state is only effective to suppress the leakage at low and high temperatures for wide fan-in domino circuits but for AND gate CHIL (clock high input low) state is preferred to reduce the leakage current. The proposed circuit technique for AND2, OR2, OR4 and OR8 circuits reduces the active power consumption by 39.6% to 57.9% and by 32.4% to 40.3% at low and high die temperatures respectively when compared to the standard dual-threshold voltage domino logic circuits.

KEYWORDS

Dual-Threshold, Domino logic, Subthreshold leakage, Gate oxide tunneling, Leakage current.

Original Source Link : http://aircconline.com/vlsics/V4N1/4113vlsics04.pdf

http://airccse.org/journal/vlsi/vol4.html

MATRIX CODE BASED MULTIPLE ERROR CORRECTION TECHNIQUE FOR N-BIT MEMORY DATA

MATRIX CODE BASED MULTIPLE ERROR CORRECTION TECHNIQUE FOR N-BIT MEMORY DATA

Sunita M.S1 and Kanchana Bhaaskaran V.S2

1VIT University, Chennai Campus, Chennai, India

PESIT, Bangalore, India

2VIT University, Chennai Campus, Chennai, India

ABSTRACT

Constant shrinkage in the device dimensions has resulted in very dense memory cells. The probability of occurrence of multiple bit errors is much higher in very dense memory cells. Conventional Error Correcting Codes (ECC) cannot correct multiple errors in memories even though many of these are capable of detecting multiple errors. This paper presents a novel decoding algorithm to detect and correct multiple errors in memory based on Matrix Codes. The algorithm used is such that it can correct a maximum of eleven errors in a 32-bit data and a maximum of nine errors in a 16-bit data. The proposed method can be used to improve the memory yield in presence of multiple-bit upsets. It can be applied for correcting burst errors wherein, a continuous sequence of data bits are affected when high energetic particles from external radiation strike memory, and cause soft errors. The proposed technique performs better than the previously known technique of error detection and correction using Matrix Codes. 

KEYWORDS

Memory testing, Error correction codes, Matrix codes, multiple error detection, multiple error correction. 

Original Source Link : http://aircconline.com/vlsics/V4N1/4113vlsics03.pdf

http://airccse.org/journal/vlsi/vol4.html

REALIZATION OF TRANSMITTER AND RECEIVER ARCHITECTURE FOR DOWNLINK CHANNELS IN 3-GPP LTE

REALIZATION OF TRANSMITTER AND RECEIVER ARCHITECTURE FOR DOWNLINK CHANNELS IN 3-GPP LTE

S. Syed Ameer Abbas#1a, J. Rahumath Nisha#1 ,M. Beril Sahaya Mary#1,S. J. Thiruvengadam#2b

aAssistant Professor, b Professor #Department of Electronics and Communication Engineering

1Mepco Schlenk Engineering College, Sivakasi- 626005, India

2Thiagarajar College of Engineering, Madurai- 625015, India

ABSTRACT

Long Term Evolution (LTE), the next generation of radio technologies designed to increase the capacity and speed of mobile networks. The future communication systems require much higher peak rate for the air interface but very short processing delay. This paper mainly focuses on to improve the processing speed and capability and decrease the processing delay of the downlink channels using the parallel processing technique. This paper proposes Parallel Processing Architecture for both transmitter and receiver for Downlink channels in 3GPP-LTE. The Processing steps include Scrambling, Modulation, Layer mapping, Precoding and Mapping to the REs in transmitter side. Similarly demapping from the REs, Decoding and Detection, Delayer mapping and Descrambling in Receiver side. Simulation is performed by using modelsim and Implementation is achieved using Plan Ahead tool and virtex 5 FPGA.Implemented results are discussed in terms of RTL design, FPGA editor, power estimation and resource estimation. 

KEYWORDS

PBCH, PMCH, PDCCH, PDSCH, PCFICH, OFDM, MBSFN, MBMS 

Original Source Link : http://aircconline.com/vlsics/V4N1/4113vlsics02.pdf

http://airccse.org/journal/vlsi/vol4.html

EFFICIENT ABSOLUTE DIFFERENCE CIRCUIT FOR SAD COMPUTATION ON FPGA

EFFICIENT ABSOLUTE DIFFERENCE CIRCUIT FOR SAD COMPUTATION ON FPGA

Jaya Koshta, Kavita Khare and M.K Gupta

Maulana Azad National Institute of Technology, Bhopal

ABSTRACT

Video Compression is very essential to meet the technological demands such as low power, less memory and fast transfer rate for different range of devices and for various multimedia applications. Video compression is primarily achieved by Motion Estimation (ME) process in any video encoder which contributes to significant compression gain.Sum of Absolute Difference (SAD) is used as distortion metric in ME process.In this paper, efficient Absolute Difference(AD)circuit is proposed which uses Brent Kung Adder(BKA) and a comparator based on modified 1’s complement principle and conditional sum adder scheme. Results shows that proposed architecture reduces delay by 15% and number of slice LUTs by 42 % as compared to conventional architecture. Simulation and synthesis are done on Xilinx ISE 14.2 using Virtex 7 FPGA.

KEYWORDS

HEVC, motion estimation, sum of absolute difference, parallel prefix adders, Brent Kung Adder.

Original Source Link : http://aircconline.com/vlsics/V10N2/10219vlsi01.pdf

http://airccse.org/journal/vlsi/vol10.html