DEVICE CHARACTERISATION OF SHORT CHANNEL DEVICES AND ITS IMPACT ON CMOS CIRCUIT DESIGN
Kiran Agarwal Gupta1, Dinesh K Anvekar2 and Venkateswarlu V3
1Department of Electronics & Communication, DSCE, Visvesvaraya Technology University, Bengaluru-78 (INDIA)
2Innovations & Six Sigma Specialist, Honeywell Technology Solutions Lab, Bengaluru-560078 (INDIA)
3VTU Extension Centre, UTL Technologies Ltd., Bengaluru-560022 (INDIA).
ABSTRACT
Semiconductor technology has reached an end in the manufacture of conventional Metal Oxide semiconductor Field Effect Transistor (MOSFET). The continuous scaling of semiconductor devices has kept pace with Moore’s law and transistors below 1µm are grouped under deep sub-micron (DSM) technology node. But this trend seem to end beyond deep sub micron levels due to main design constraints such as short channel effects (SCE) , and variations in process design parameters leading to high leakage currents. Silicon material processes technology has undergone a change in process material and technology beyond 180nm node. For DSM technology nodes leakage current dominates the devices. Circuit designing using MOSFETs at deep sub micron levels, needs a careful study of the behaviour of short channel devices for the parameter variations such as threshold voltage, channel length leading to high leakage currents and poor performance of devices. In this paper we have presented the behaviour of NMOS metal oxide semiconductor field effect transistor (MOSFETs) for 90nm technology node in detail and finally compared with 180nm and 45nm nodes. The simulations have been carried out using libraries from TSMC foundry and the device has been simulated using Virtuoso Cadence Spectre Simulator version 6.1.5 with HSPICE.
KEYWORDS
MOSFETs; Technology node; process parameter variations; Short Channel Effects; DIBL; leakage current; low power;
Original Source Link : http://aircconline.com/vlsics/V3N5/3512vlsics14.pdf
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