A High-Speed, Low Power Consumption Positive Edge Triggered D Flip-Flop for High Speed Phase Frequency Detector in 180 nm CMOS Technology

A High-Speed, Low Power Consumption Positive Edge Triggered D Flip-Flop for High Speed Phase Frequency Detector in 180 nm CMOS Technology

Prof. R .H. Talwekar, Prof. (Dr.) S.S Limaye

Deptt. Of Electronics and Telecommunication, DIMAT, Raipur.

Deptt. Of Electronics and Telecommunication, JIT, Nagpur.

ABSTRACT

A high speed low power consumption positive edge triggered Delayed (D) flip-flop was designed for increasing the speed of counter in Phase locked loop, using 180 nm CMOS technology. The designed counter has been used in the divider chip of the phase locked loop. A divide counter is required in the feedback loop to increase the VCO frequency above the input reference frequency. The proposed circuit is faster than conventional circuit as it has fast reset operation. The circuit consumes less power as it prevents short circuit power consumption. The circuit operates at 1.8V power supply. This work has been used in the design. of 2.4 GHz CMOS PLL targeting OFDM application. The CMOS based fast D-ff circuit has designed and simulated by Virtuoso tool of CADENCE spectre

KEYWORDS

Phase locked loop (PLL), Delayed flip-flop (D-ff), Phase frequency detector (PFD),True signal phase clock (TSPC), Voltage controlled oscillator (VCO), Charge pump (CP), Divider (Div), Low pass filter (LPF). 

Original Source Link : http://aircconline.com/vlsics/V3N5/3512vlsics13.pdf

http://airccse.org/journal/vlsi/vol3.html