DESIGN & ANALYSIS OF A CHARGE RE-CYCLE BASED NOVEL LPHS ADIABATIC LOGIC CIRCUITS FOR LOW POWER APPLICATIONS

DESIGN & ANALYSIS OF A CHARGE RE-CYCLE BASED NOVEL LPHS ADIABATIC LOGIC CIRCUITS FOR LOW POWER APPLICATIONS

Sanjeev Rai1, Govind Krishna Pal2, Ram Awadh Mishra3 and Sudarshan Tiwari4

1Department of Electronics & Communication Engineering, Motilal Nehru National Institute of Technology, Allahabad, India

2Apache Design Solutions, Noida, India

3Department of Electronics & Communication Engineering, Motilal Nehru National Institute of Technology, Allahabad, India

4Director National Institute of Technology, Raipur, Chhatisgarh, India

ABSTRACT

This paper focuses on principles of adiabatic logic, its classification and comparison of various adiabatic logic designs. An attempt has been made in this paper to modify 2PASCL (Two Phase Adiabatic Static CMOS Logic) adiabatic logic circuit to minimize delay of the different 2PASCL circuit designs. This modifications in the circuits leads to improvement of Power Delay Product (PDP) which is one of the figure of merit to optimize the circuit with factors like power dissipation and delay of the circuit. This paper investigates the design approaches of low power adiabatic gates in terms of energy dissipation and uses of Simple PN diode instead of MOS diode which reduces the effect of Capacitances at high transition and power clock frequency. A computer simulation using SPECTRE from Cadence is carried out on different adiabatic circuits, such as Inverter, NAND, NOR, XOR and 2:1 MUX.

KEYWORDS

Adiabatic logic, Low-power, Two phase clocked, Energy recovery, Split-level, Diode based logic, Power Delay Product (PDP), LPHS (Low Power High Speed). 

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