AN EFFICIENT APPROACH FOR FOUR-LAYER CHANNEL ROUTING IN VLSI DESIGN

AN EFFICIENT APPROACH FOR FOUR-LAYER CHANNEL ROUTING IN VLSI DESIGN

Ajoy Kumar Khan1, Bhaskar Das2 and Tapas Kumar Bayen3

1Department of Information Technology, Assam University, Silchar, India

2Department of Information Technology, Assam University, Silchar, India

3Department of Computer Science and Engineering, N. I. S. T, Berhampur, India

ABSTRACT

Channel routing is a key problem in VLSI physical design. The main goal of the channel routing problem is to reduce the area of an IC chip. If we concentrate on reducing track number in channel routing problem then automatically the area of an IC chip will be reduced. Here, we propose a new algorithm to reduce the number of tracks using four layers (two horizontal layers and two vertical layers). To be more specific, through this algorithm we convert a two-layer channel routing problem into a four-layer channel routing problem using VCG of the channel. Next, we show the experimental results and graphical structure of that solution.

KEYWORDS

Track, Channel routing, Manhattan routing model, VCG & Merging. 

Original Source Link : http://aircconline.com/vlsics/V3N5/3512vlsics12.pdf

http://airccse.org/journal/vlsi/vol3.html