DESIGN OF A RECONFIGURABLE DSP PROCESSOR WITH BIT EFFICIENT RESIDUE NUMBER SYSTEM1
Chaitali Biswas Dutta1, Partha Garai2 and Amitabha Sinha3
1Research Scholar, Dept of CSE, University of Kalyani, India
Assistant Professor, Dept of Computer Application, Girijananda Chowdhury Institute of Management & Technology, Guwahati, India
2Machine Intelligence Unit, Indian Statistical Institute, Kolkata, 203, BT Road, Kolkata - 700108, India
3School of Information Technology, West Bengal University of Technology, BF-142, Sector-1, Salt Lake City, Kolkata-700064, India
ABSTRACT
Residue Number System (RNS), which originates from the Chinese Remainder Theorem, offers a promising future in VLSI because of its carry-free operations in addition, subtraction and multiplication. This property of RNS is very helpful to reduce the complexity of calculation in many applications. A residue number system represents a large integer using a set of smaller integers, called residues. But the area overhead, cost and speed not only depend on this word length, but also the selection of moduli, which is a very crucial step for residue system. This parameter determines bit efficiency, area, frequency etc. In this paper a new moduli set selection technique is proposed to improve bit efficiency which can be used to construct a residue system for digital signal processing environment. Subsequently, it is theoretically proved and illustrated using examples, that the proposed solution gives better results than the schemes reported in the literature. The novelty of the architecture is shown by comparison the different schemes reported in the literature. Using the novel moduli set, a guideline for a Reconfigurable Processor is presented here that can process some predefined functions. As RNS minimizes the carry propagation, the scheme can be implemented in Real Time Signal Processing & other fields where high speed computations are required.
Original source Link : http://aircconline.com/vlsics/V3N5/3512vlsics15.pdf
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