HIGH SPEED CONTINUOUS-TIME BANDPASS Σ∆ ADC FOR MIXED SIGNAL VLSI CHIPS

HIGH SPEED CONTINUOUS-TIME BANDPASS Σ∆ ADC FOR MIXED SIGNAL VLSI CHIPS

P.A.HarshaVardhini1 and Dr.M.MadhaviLatha2

1Ph.D Scholar, Dept. of ECE, J.N.T.U, Hyderabad, A.P, India.

2Professor and Head, Dept. of ECE, J.N.T.U, Hyderabad, A.P, India.

ABSTRACT

With the unremitting progress in VLSI technology, there is a commensurate increase in performance demand on analog to digital converter and are now being applied to wideband communication systems. sigma Delta (Σ∆) converter is a popular technique for obtaining high resolution with relatively small bandwidth. Σ∆ ADCs which trade sampling speed for resolution can benefit from the speed advantages of nm-CMOS technologies. This paper compares various Band pass sigma Delta ADC architectures, both continuous-time and discrete-time, in respect of power consumption and SNDR. Design of 2nd order multibit continuous time band pass Σ∆ modulator is discussed with the methods to resolve DAC non-idealities.

KEYWORDS

CMOS, Over sampling, Noise shaping, Sigma Delta Modulation, Bandpass Σ∆ modulator, Dynamic element matching, Data weighted averaging

Original Source Link : http://aircconline.com/vlsics/V3N2/3212vlsics06.pdf

http://airccse.org/journal/vlsi/vol3.html

Microcontroller Based Testing of Digital IP-Core

Microcontroller Based Testing of Digital IP-Core

Amandeep Singh1 and Balwinder Singh2

1-2Acadmic and Consultancy Services Division, Centre for Development of Advanced Computing(C-DAC), Mohali, India

ABSTRACT

Testing core based System on Chip [1] is a challenge for the test engineers. To test the complete SOC at one time with maximum fault coverage, test engineers prefer to test each IP-core separately. At speed testing using external testers is more expensive because of gigahertz processor. The purpose of this paper is to develop cost efficient and flexible test methodology for testing digital IP-cores [2]. The prominent feature of the approach is to use microcontroller to test IP-core. The novel feature is that there is no need of test pattern generator and output response analyzer as microcontroller performs the function of both. This approach has various advantages such as at speed testing, low cost, less area overhead and greater flexibility since most of the testing process is based on software.

KEYWORDS

Microcontroller, FPGA, Testing, TMR, SOC

Original Source Link : http://aircconline.com/vlsics/V3N2/3212vlsics05.pdf

http://airccse.org/journal/vlsi/vol3.html

CELL STABILITY ANALYSIS OF CONVENTIONAL 6T DYNAMIC 8T SRAM CELL IN 45NM TECHNOLOGY

CELL STABILITY ANALYSIS OF CONVENTIONAL 6T DYNAMIC 8T SRAM CELL IN 45NM TECHNOLOGY

K. Dhanumjaya1 , M. Sudha2 , Dr.MN.Giri Prasad3 , Dr.K.Padmaraju4

1Research Scholar, Jawaharlal Nehru Technological University, Anantapur, AP, INDIA

2PG Student, Jawaharlal Nehru Technological University, Anantapur, AP, INDIA

3Professor, Jawaharlal Nehru Technological University, Anantapur, AP, INDIA

4Professor, Jawaharlal Nehru Technological University, Kakinada, AP, INDIA

ABSTRACT:-

A SRAM cell must meet requirements for operation in submicron/nano ranges. The scaling of CMOS technology has significant impact on SRAM cell -- random fluctuation of electrical characteristics and substantial leakage current. In this paper we present dynamic column based power supply 8T SRAM cell and comparing the proposed SRAM cell with respect to conventional SRAM 6T in various aspects. To verify read stability and write ability analysis we use N-curve metric. Simulation results affirmed that proposed 8T SRAM cell achieved improved read stability, read current, and leakage current in 45nm Technology comparing with conventional 6T SRAM using cadence virtuoso tool.

Key Words:-

SRAM, Leakage Current, N-curve, Read stability, Write-ability, Cadence, Virtuoso, 45nm Technology

Original source Link : http://aircconline.com/vlsics/V3N2/3212vlsics04.pdf

http://airccse.org/journal/vlsi/vol3.html

A Bus Encoding Method for Crosstalk and Power Reduction in RC Coupled VLSI Interconnects

A Bus Encoding Method for Crosstalk and Power Reduction in RC Coupled VLSI Interconnects

S.K.Verma1 and B.K.Kaushik2

1Department of Computer Science and Engineering, G. B. Pant Engineering College, Pauri-Garhwal, INDIA

2Department of Electronics and Computer Engineering, Indian Institute of Technology, Roorkee, INDIA

ABSTRACT

The performance factors such as propagation delay, power dissipation and crosstalk in RC modelled interconnects are major design issues for the System on-chip (SoC) designs in current Deep Submicron (DSM) era. The crosstalk effect is a consequence of coupling and switching activities that is encountered when there is a transition as compared to previous state of wire and or when there are transitions in adjacent wires. Therefore, minimization or elimination of switching and coupling activities is crucial in enhancing the performance of SoC designs. There are several methods for the reduction of power dissipation, crosstalk and delay. The encoding method is most effective and popular method for enhancing the behaviour of on-chip buses. This paper proposes encoding scheme to achieve overall reduction in transitions. The reduction in transition improves the performance in terms of reduced power dissipation, coupling activity and delay in on-chip buses. This encoding method is implemented using VHDL. The result evidently demonstrates reduction in transitions which consequently improves the overall performance of on-chip buses.

Keywords

Coupling, VLSI, SoC, Bus Encoding, Interconnects 

Original Source Link : http://aircconline.com/vlsics/V3N2/3212vlsics03.pdf

http://airccse.org/journal/vlsi/vol3.html

Finite State Machine based Vending Machine Controller with Auto-Billing Features

Finite State Machine based Vending Machine Controller with Auto-Billing Features

Ana Monga1, Balwinder Singh2

1,2Academic and Consultancy Services-Division,Centre for Development of Advanced Computing(C-DAC), Mohali, India

ABSTRACT

Nowadays, Vending Machines are well known among Japan, Malaysia and Singapore. The quantity of machines in these countries is on the top worldwide. This is due to the modern lifestyles which require fast food processing with high quality. This paper describes the designing of multi select machine using Finite State Machine Model with Auto-Billing Features. Finite State Machine (FSM) modelling is the most crucial part in developing proposed model as this reduces the hardware. In this paper the process of four state (user Selection, Waiting for money insertion, product delivery and servicing) has been modelled using MEALY Machine Model. The proposed model is tested using Spartan 3 development board and its performance is compared with CMOS based machine.

KEYWORDS

FSM; VHDL; Vending Machine; FPGA Spartan 3 development board; 

Original Source Link : http://aircconline.com/vlsics/V3N2/3212vlsics02.pdf

http://airccse.org/journal/vlsi/vol3.html

A SYSTEMC/SIMULINK CO-SIMULATION ENVIRONMENT OF THE JPEG ALGORITHM

A SYSTEMC/SIMULINK CO-SIMULATION ENVIRONMENT OF THE JPEG ALGORITHM

Walid Hassairi, Moncef Bousselmi, Mohamed Abid and Carlos Valderrama

UMons University of Mons, Electronics & Microelectronics Dpt., Mons, Belgium

Laboratory CES, National School of Engineers of Sfax, Tunisia 

ABSTRACT

In the past decades, many factors have been continuously increasing like the functionality of embedded systems as well as the time-to-market pressure has been continuously increasing. Simulation of an entire system including both hardware and software from early design stages is one of the effective approaches to improve the design productivity. A large number of research efforts on hardware/software (HW/SW) co-simulation have been made so far. Real-time operating systems have become one of the important components in the embedded systems. However, in order to validate function of the entire system, this system has to be simulated together with application software and hardware. Indeed, traditional methods of verification have proven to be insufficient for complex digital systems. Register transfer level test-benches have become too complex to manage and too slow to execute. New methods and verification techniques began to emerge over the past few years. Highlevel test-benches, assertion-based verification, formal methods, hardware verification languages are just a few examples of the intense research activities driving the verification domain. 

KeyWord 

Design, Computer-Aided Design (CAD), Testing, Reliability, Fault-Tolerance, Emerging Technologies, Communications, Video, Security, Sensor Networks, Biological and 

Wireless Communications

Original Source Link : http://aircconline.com/vlsics/V3N2/3212vlsics01.pdf

http://airccse.org/journal/vlsi/vol3.html

BUS ENCODER FOR CROSSTALK AVOIDANCE IN RLC MODELED INTERCONNECTS

BUS ENCODER FOR CROSSTALK AVOIDANCE IN RLC MODELED INTERCONNECTS

G. Nagendra Babu1, Deepika Agarwal2, B. K. Kaushik3 and S. K. Manhas4

Department of Electronics and Computer Engineering, Indian Institute of Technology, Roorkee -247667, INDIA

ABSTRACT

Most of the encoding methods proposed in recent years have dealt with only RC modeled VLSI interconnects. For deep submicron technologies (DSM), on-chip inductive effects have increased due to faster clock speeds, smaller signal rise times and longer length of on-chip interconnects. All these issues raise the concern for crosstalk, propagation delay and power dissipation of overall. Therefore, this research work introduces an efficient Bus Encoder using Bus Inverting (BI) method. The proposed design dramatically reduces both crosstalk and power dissipation in RLC modeled interconnects which makes it suitable for current high-speed low-power VLSI interconnects. The proposed model demonstrates an overall reduction of power dissipation and crosstalk induced delay by 55.43% and 45.87%, respectively.

KEYWORDS

Inductance effects, Bus-invert, Crosstalk, Power dissipation. 

Original Source Link : http://aircconline.com/vlsics/V3N1/3112vlsics15.pdf

http://airccse.org/journal/vlsi/vol3.html

Faster Interleaved Modular Multiplier Based on Sign Detection

Faster Interleaved Modular Multiplier Based on Sign Detection

Mohamed A. Nassar, and Layla A. A. El-Sayed

Department of Computer and Systems Engineering, Alexandria University, Alexandria, Egypt

Abstract

Data Security is the most important issue nowadays. A lot of cryptosystems are introduced to provide security. Public key cryptosystems are the most common cryptosystems used for securing data communication. The common drawback of applying such cryptosystems is the heavy computations which degrade performance of a system. Modular multiplication is the basic operation of common public key cryptosystems such as RSA, Diffie-Hellman key agreement (DH), ElGamal and ECC. Much research is now directed to reduce overall time consumed by modular multiplication operation. Abd-el-fatah et al. introduced an enhanced architecture for computing modular  ultiplication of two large numbers X and Y modulo given M. In this paper, a modification on that architecture is introduced. The proposed design computes modular multiplication by scanning two bits per iteration instead of one bit. The proposed design for 1024-bit precision reduced overall time by 38% compared to the design of Abd-el-fatah et al.

Keywords:

efficient architecture, carry-save adder, sign detection, sign estimation technique, modular multiplication,FPGA, RSA. 

Original Source Link : http://aircconline.com/vlsics/V3N1/3112vlsics14.pdf

http://airccse.org/journal/vlsi/vol3.html

Area, Delay and Power Comparison of Adder Topologies

Area, Delay and Power Comparison of Adder Topologies

R. Uma1,Vidya Vijayan2, M. Mohanapriya2 and Sharon Paul2, 

1Pondicherry University, India and 2Rajiv Gandhi College of Engineering and Technology, India

Abstract

Adders form an almost obligatory component of every contemporary integrated circuit. The prerequisite of the adder is that it is primarily fast and secondarily efficient in terms of power consumption and chip area. This paper presents the pertinent choice for selecting the adder topology with the tradeoff between delay, power consumption and area. The adder topology used in this work are ripple carry adder, carry lookahead adder, carry skip adder, carry select adder, carry increment adder, carry save adder and carry bypass adder. The module functionality and performance issues like area, power dissipation and propagation delay are analyzed at 0.12µm 6metal layer CMOS technology using microwind tool.

Keywords : 

Ripple Carry Adder, Carry Save Adder, Carry Increment Adder, Carry Select Adder. 

Original Source Link : http://aircconline.com/vlsics/V3N1/3112vlsics13.pdf

http://airccse.org/journal/vlsi/vol3.html

A 3 – 14 GHZ LOW NOISE AMPLIFIER FOR ULTRA WIDE BAND APPLICATIONS

A 3 – 14 GHZ LOW NOISE AMPLIFIER FOR ULTRA WIDE BAND APPLICATIONS

Vaithianathan Venkatesan1,*, Raja Janakiraman2 and Srinivasan Raj3 Aishwarya Prabakaran4 , Anupreethi Balaji Ranganathan5, Divya Santhanam6

1,4,5,6Department of Electronics and Communication Engineering, Sri Sivasubramaniya Nadar College of Engineering, Chennai, India

2Department of Electronics and Communication Engineering, Anna University of Technology, Tiruchirappali, India

3Department of Information Technology, Sri Sivasubramaniya Nadar College of Engineering, Chennai, India

ABSTRACT

This paper presents an ultra wide band (UWB) low noise amplifier (LNA) with very high gain, better input matching, low noise figure, better linearity and low power consumption. A dual source degenerated resistive current reuse is used as an input stage and a cascode stage with shunt-series peaking is used to enhance the bandwidth and reverse isolation. The proposed LNA achieves a peak power gain of 20.92 dB at 9 GHz while achieving a gain greater than 20.3 dB over 3 – 14 GHz bandwidth. The achieved noise figure is in the range of 3.72 – 4.78 dB, while the input matching and the output matching are kept below – 9 dB and –10 dB respectively. The reverse isolation is below –52 dB throughout the entire band. This LNA ensures better linearity with an IIP3 of 4 dBm at 9 GHz with very low power consumption of 5.876 mW at 1 V supply.

KEYWORDS

Dual Source Degenerated Current Reuse, Shunt-Series Peaking, Power Gain, Noise Figure, Input Third Order Intercept Point (IIP3) 

Original Source Link : http://aircconline.com/vlsics/V3N1/3112vlsics12.pdf

http://airccse.org/journal/vlsi/vol3.html

VOLTAGE STACKING FOR SIMPLIFYING POWER MANAGEMENT IN ASYNCHRONOUS CIRCUITS

VOLTAGE STACKING FOR SIMPLIFYING POWER MANAGEMENT IN ASYNCHRONOUS CIRCUITS

Andrew Suchanek1, Zhong Chen2 and Jia Di1

1Computer Science and Computer Engineering Department, University of Arkansas, Fayetteville, Arkansas, USA

2Electrical Engineering Department, University of Arkansas,Fayetteville, Arkansas, USA 

ABSTRACT

Multiple power domains on a single integrated circuit (IC) are becoming more common due to the increasing complexity of systems on chips (SoCs) as process nodes continue to get smaller. Supplying the correct voltage to each domain requires the use of multiple voltage converters that occupy substantial space either on-chip or off-chip and introduce additional power loss in the conversions. In this paper, an asynchronous paradigm called Multi-Threshold NULL Convention Logic (MTNCL) is used to create a “stacked” architecture that reduces the number of converters needed and thereby mitigating the aforementioned problems. In this architecture, the MTNCL circuits are stacked between a multiple of VDD and GND, where simple control mechanisms alleviate the induced dynamic range fluctuation problem. The GLOBALFOUNDRIES 32nm Silicon-on-Insulator (SOI) CMOS process is used to evaluate and analyze the theoretical effects of parasitic extracted physical implementations in stacking different circuits running different workloads. These results show that the “stacked” architecture introduce negligible overhead compared to the operation of the individual circuits while substantially alleviating the need for voltage converters, which in turn reduces the overall power consumption of the system. 

KEYWORDS

Voltage stacking; power management; asynchronous; MTNCL

Original Source Link : http://aircconline.com/vlsics/V9N4/9418vlsi02.pdf

http://airccse.org/journal/vlsi/current.html

FIVE-TRANSISTOR SINGLE-PORT SRAM BIT CELL WITH HIGH SPEED AND LOW STANDBY CURRENT

FIVE-TRANSISTOR SINGLE-PORT SRAM BIT CELL WITH HIGH SPEED AND LOW STANDBY CURRENT

Chien-Cheng Yu1,3*, Ming-Chuen Shiau2, and Ching-Chih Tsai3

1&2Department of Electronic Engineering, Hsiuping University of Science and Technology,Taichung City, Taiwan

3Department of Electrical Engineering, National Chung Hsing University Taichung City, Taiwan

ABSTRACT

In this paper, a new five-transistor (5T) single-port Static Random Access Memory (SRAM) cell with voltage assist is proposed. Amongst them, a word line suppression circuit is designed to provide a voltage of the respective connected word line signal in a selected row cells lower than the power supply voltage VDD by a threshold voltage during a read operation, thereby to improve the read/write-ability of the cell. In addition, a voltage control circuit is coupled to the sources corresponding to driver transistors of each row memory cells. This configuration is aimed to control the source voltages of driver transistors under different operating modes. Specifically, during a read operation, a two-stage reading mechanism is engaged to increase the reading speed. Simulation results for the proposed cell design confirm that there is a conspicuous improvement in reading speed and power saving over the conventional SRAM cells, and fast writing also can be achieved.

KEYWORDS

Single-port, Static random access memory, Assist circuitry, Voltage control circuit, Standby start-up circuit

Original Source Link : http://aircconline.com/vlsics/V9N4/9418vlsi01.pdf

http://airccse.org/journal/vlsi/current.html

Current Issue

Current Issue

August 2018, Volume 9, Number 4

Five-Transistor Single-Port SRAM Bit Cell with Hight Speed and Low Standby Current

Chien-Cheng Yu1,2, Ming-Chuen Shiau1 and Ching-Chih Tsai2, 

1Hsiuping University of Science and Technology, Taiwan and 

2National Chung Hsing University, Taiwan

http://aircconline.com/vlsics/V9N4/9418vlsi01.pdf

Voltage Stacking for Simplifying Power Management in Asynchronous Circuits

Andrew Suchanek, Zhong Chen and Jia Di, 

University of Arkansas, USA

http://aircconline.com/vlsics/V9N4/9418vlsi02.pdf