MODELING OF BUILT-IN POTENTIAL VARIATIONS OF CYLINDRICAL SURROUNDING GATE (CSG) MOSFETS
Santosh Kumar Gupta1 and S. Baishya2
Department of Electronics & Communication Engineering, National Institute of Technology Silchar, Assam – 788 010, INDIA
ABSTRACT
Due to aggressive scaling of MOSFETs the parasitic fringing field plays a major role in deciding its characteristics. These fringing fields are now not negligible and should be taken into account for deriving the MOSFET models. Due to this fringing field effect there are some charges induced in the source/drain extension regions which will change the potential barrier at the source-channel from its theoretical nominal values. In this paper an attempt has been made to model variation of built-in potential variation for a cylindrical surrounding gate MOSFET. The model has been verified to be working in good agreement with the variations of gate length and channel radius.
KEYWORDS
Barrier lowering, cylindrical surround gate (CSG) MOSFET, fringing field, short channel effects (SCEs)
Original Source Link : http://aircconline.com/vlsics/V3N5/3512vlsics06.pdf
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