EFFECT OF EQUAL AND MISMATCHED SIGNAL TRANSITION TIME ON POWER DISSIPATION IN GLOBAL VLSI INTERCONNECTS
Devendra Kumar Sharma*, Brajesh Kumar Kaushik#, and R.K.Sharma$
*Department of ECE, Meerut Institute of Engineering and Technology, Meerut, INDIA
#Department of Electronics and Computer Engineering, Indian Institute of Technology, Roorkee, INDIA
$Department of ECE, National Institute of Technology, Kurukshetra, Haryana, INDIA
ABSTRACT
High density chips have introduced problems like crosstalk noise and power dissipation. The mismatching in transition time of the inputs occurs because different lengths of interconnects lead to different parasitic values. This paper presents the analysis of the effect of equal and unequal (mismatched) transition time of inputs on power dissipation in coupled interconnects. Further, the effect of signal skew on transition time is analysed. To demonstrate the effects, a model of two distributed RLC lines coupled capacitively and inductively is taken into consideration. Each interconnect line is 4mm long and terminated by capacitive load of 30fF. The analysis is carried out for simultaneously switching lines. The results are obtained through SPICE simulations and waveforms are generated.
KEYWORDS
Equal / Unequal rise time, Power dissipation, simultaneous switching, Signal Skew
Original Source Link : http://aircconline.com/vlsics/V3N4/3412vlsics10.pdf
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