QUATERNARY LOGIC AND APPLICATIONS USING MULTIPLE QUANTUM WELL BASED SWSFETS
P. Gogna1,2, M. Lingalugari2, J. Chandy2, E. Heller3, E-S. Hasaneen4 and F. Jain2
1Intel Massachusetts Corp, Hudson, MA, USA
2Electrical and Computer Engineering, University of Connecticut, Storrs, CT, USA
3RSoft Design Group, Ossining, NY, 4Electrical Engineering, Minia University, Egypt
ABSTRACT
This paper presents Spatial Wavefunction-Switched Field-Effect Transistors (SWSFET) to implement efficient quaternary logic and arithmetic functions. Various quaternary logic gates and digital building blocks are presented using SWSFETs. In addition, arithmetic operation with full adder using novel logic algebra is also presented. The SWSFET based implementation of digital logic, cache and arithmetic block results in up to 75% reduction in transistor count and up to 50% reduction in data interconnect densities. Simulations of quaternary logic gates using the BSIM equivalent models for SWSFET channels are also described.
KEYWORDS
Quaternary Logic, Multi-Channel, Nanotechnology, SWSFETs
Original Source Link : http://aircconline.com/vlsics/V3N5/3512vlsics03.pdf
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