STAND-BY LEAKAGE POWER REDUCTION IN NANOSCALE STATIC CMOS VLSI MULTIPLIER CIRCUITS USING SELF ADJUSTABLE VOLTAGE LEVEL CIRCUIT
Deeprose Subedi1 and Eugene John2
1Student, Department of Electrical and Computer Engineering, University of Texas at San Antonio, San Antonio, TX USA.
2Professor, Department of Electrical and Computer Engineering, University of Texas at San Antonio, San Antonio, TX USA.
ABSTRACT
In this paper, we performed the comparative analysis of stand-by leakage (when the circuit is idle), delay and dynamic power (when the circuit switches) of the three different parallel digital multiplier circuits implemented with two adder modules and Self Adjustable Voltage level circuit (SVL). The adder modules chosen were 28 transistor-conventional CMOS adder and 10 transistor- Static Energy Recovery CMOS adder (SERF) circuits. The multiplier modules chosen were 4Bits Array, 4bits Carry Save and 4Bits Baugh Wooley multipliers. At first, the circuits were simulated with adder modules without applying the SVL circuit. And secondly, SVL circuit was incorporated in the adder modules for simulation. In all the multiplier architectures chosen, less standby leakage power was observed being consumed by the SERF adder based multipliers applied with SVL circuit. The stand-by leakage power dissipation is 1.16µwatts in Bits array multiplier with SERF Adder applied with SVL vs. 1.39µwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit. It is 1.16µwatts in Carry Save multiplier with SERF Adder applied with SVL vs. 1.4µwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit. It is 1.67µwatts in Baugh Wooley multiplier with SERF Adder applied with SVl circuit vs. 2.74µwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit.
KEYWORDS
10 Transistor SERF Adder, SVL Circuit, Stand-by Leakage Power, Dynamic Power, Delay, Low Power Design, Sub-micron Regimes.
Original Source Link : http://aircconline.com/vlsics/V3N5/3512vlsics01.pdf
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