LOW POWER DYNAMIC BUFFER CIRCUITS

LOW POWER DYNAMIC BUFFER CIRCUITS

Amit Kumar Pandey, Ram Awadh Mishra and Rajendra Kumar Nagaria

Department of Electronics and Communication, M.N.N.I.T, Allahabad, India

ABSTRACT

In this paper we propose two buffer circuits for footed domino logic circuit. It minimizes redundant  switching at the output node. These circuits prevent propagation of precharge pulse to the output node during precharge phase which saves power consumption. Simulation is done using 0.18µm CMOS technology. We have calculated the power consumption, delay and power delay product of proposed circuits and compared the results with existing standard domino circuit for different logic function, loading condition, clock frequency, temperature and power supply. Our proposed circuits reduce power consumption and power delay product as compared to standard domino circuit.

KEYWORDS

Buffer, Dynamic circuit, Power consumption, Delay, Precharge pulse. 

Original Source Link : http://aircconline.com/vlsics/V3N5/3512vlsics05.pdf

http://airccse.org/journal/vlsi/vol3.html