VHDL Design for Image Segmentation using Gabor filter for Disease Detection

International Journal of VLSI design & Communication Systems (VLSICS)

Rucha R. Thakur1, Swati R. Dixit2 and Dr.A.Y.Deshmukh3

1Department of Electronics & Telecommunication Engineering, PG Student,G.H.Raisoni College of Engineering, Nagpur, India

2Department of Electronics & Telecommunication Engineering, Research Scholar,G.H.Raisoni College of Engineering, Nagpur, India

3Department of Electronics Engineering, Professor, G.H.Raisoni College of Engineering, Nagpur, India

Abstract

Tonsillitis, Tumor and many more skin diseases can be detected in its early-state and can be cured. For this a new idea for efficient Gabor filter design with improved data transfer rate, efficient noise reduction, less power consumption and reduced memory usage is proposed in this paper. The filter design is suitable for detecting the early stages of disease using textural properties of anatomical structures. The code for Gabor filter will be developed in VHDL using Modelsim and then implemented on SPARTAN-3E FPGA kit. These systems must provide both highly accurate and extremely fast processing of large amounts of image data.

Keywords

Segmentation, Medical image, Gabor algorithm, CORDIC algorithm, FPGA

Original Source Link : http://aircconline.com/vlsics/V3N2/3212vlsics18.pdf

http://airccse.org/journal/vlsi/vol3.html

Power consumption reduction in a SDR based wireless communication system using partial reconfigurable FPGA

Power consumption reduction in a SDR based wireless communication system using partial reconfigurable FPGA

1 Neenu Joseph, 2 Dr. P Nirmal Kumar

1Research Scholar, Department of ECE Anna University, Chennai,

2Associate Professor, Department of ECE, Anna University, Chennai,

ABSTRACT

The increase in the consumer demand and the exponential growth for wireless systems, which enables consumer to communicate in any place by means of information, has in turn led to the emergence of many portable wireless communication products. The present research works primarily targets to integrate as much as signal processing applications in a single portable device. Since integration through software applications compromises system speed, integration through hardware will be the better compliment. Software Defined Radio (SDR) Technology yields to achieve this small form factor system while keeping power consumption under the limit. SDR enables soft changeable system functionality, such as receiver demodulation technique .In this implementation two type modulation techniques are used, ASK and FSK. The flexibility of changing the receiver functionality in runtime is usually attained by FPGA. However, using a complete FPGA for reconfiguration of a particular functionality is not an efficient method in terms of power consumption and switching time. We proposed a SDR architecture using a recent advancement in FPGAs, called Partial Reconfiguration (PR). PR helps to change certain portion of FPGA, while the rest keeps functioning. It also reduces the total hardware usage and hence the power. The different demodulation technique and other signal processing application from an external memory unit can be loaded into FPGA PR modules while the other parts of FPGA doing a constant data processing.

KEYWORDS

Partial Reconfiguration in FPGA, Modulation Techniques, Wireless communication, CDMA, GSM, ASK, PSK, AM, FM

Original Source Link : http://aircconline.com/vlsics/V3N2/3212vlsics17.pdf

http://airccse.org/journal/vlsi/vol3.html

Design of Near-Threshold CMOS Logic Gates

Design of Near-Threshold CMOS Logic Gates

N. Geetha Rani1, N. Praveen Kumar2, Dr. B. Dr. B. Stephen Charles 3Dr. P. Chandrasekhar Reddy 4 S.Md.Imran Ali 5

1Assistant Professor, ECE Department, Stanley Stephen College of Engineering & Technology, Kurnool, A.P., India

2Assistant Professor, ECE Department, Stanley Stephen College of Engineering & Technology, Kurnool, A.P., India

3Professor, ECE Department, Stanley Stephen College of Engineering & Technology,Kurnool, A.P., India 

4Professor, ECE Department, JNTUH College of Engineering,Hyderabad, A.P., India

5 Assistant Professor, ECE Department, Stanley Stephen College of Engineering &Technology, Kurnool, A.P., India 

ABSTRACT

Numerous efforts have made to balance the tradeoff between power consumption, area and speed of a design. While studying the design at the two extreme ends of the design spectrum, namely the ultra-low power with acceptable performance at one end and high performance with power within limit at the other has not made. One solution to achieve the ultra-low power consumption is to operate the design in subthreshold region. The use of sub-threshold circuit designing in fast and energy efficient circuits is always needed in electronics industry especially in DSP, image processing and arithmetic units in microprocessors, where the low power is the primary concern and the delay can be tolerated. We design a simple CMOS inverter in weak inversion region (sub-threshold) and compare the power consumption with strong inversion region using Cadence 0.18µm Technology.

KEYWORDS:

Ultra low power, Sub-Threshold Region, CMOS

Original Scource Link : http://aircconline.com/vlsics/V3N2/3212vlsics16.pdf

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THRESHOLD VOLTAGE CONTROL SCHEMES IN FINFETS

THRESHOLD VOLTAGE CONTROL SCHEMES IN FINFETS

V. Narendar1, Ramanuj Mishra2, Sanjeev Rai3, Nayana R4 and R. A. Mishra5

Department of Electronics & Communication Engineering, MNNIT-Allahabad Allahabad-211004, (U.P)-India

ABSTRACT

Conventionally polysilicon is used in MOSFETs for gate material. Doping of polysilicon and thus changing the workfunction is carried out to change the threshold voltage. Additionally polysilicon is not favourable as gate material for smaller dimensional devices because of its high thermal budget process and degradation due to the depletion of the doped polysilicon, thus metal gate is preferred over polysilicon. Control of workfunction in metal gate is a challenging task. The use of metal alloys as gate materials for variable gate workfunction has been already reported in literature. In this work various threshold voltage techniques has been analyzed and a novel aligned dual metal gate technique is proposed for threshold voltage control in FinFETs.

KEYWORDS

Dual-Metal gate (DMG), FinFET, Gate Workfunction, Independent-Gate (IG), Short channel Effects (SCEs), Threshold voltage (VT).

Original source Link : http://aircconline.com/vlsics/V3N2/3212vlsics15.pdf

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DESIGN AND NOISE OPTIMIZATION OF RF LOW NOISE AMPLIFIER FOR IEEE STANDARD 802.11A WLAN

DESIGN AND NOISE OPTIMIZATION OF RF LOW NOISE AMPLIFIER FOR IEEE STANDARD 802.11A WLAN

Ravinder Kumar1 , Munish Kumar2, and Viranjay M. Srivastava1

1Department of Electronics and Communication Engineering, Jaypee University of Information Technology, Solan-173234, India.

2Department of Electronics and Communication Engineering, Guru Jambheshwar University of Science and Technology, Hisar-125001, India

ABSTRACT

Low noise amplifier is the front end block of radio-frequency receiver system. Its design required various characteristics such as power gain, noise figure, insertion losses and power consumption. In this paper we have proposed a single stage low noise amplifier design with high gain and low noise using inductive source degeneration topology for frequency range of 3 GHz to 7 GHz and also use the active biasing devices. A range of devices like inductors and capacitors are used to achieve 50 Ω input impedance with a low noise factor. The design process is simulated process is using Advance Design System (ADS) and implemented in TSMC 0.18 µm CMOS technology. A single stage low noise amplifier has a measured forward gain 25.4 dB and noise figure 2.2 dB at frequency 5.0 GHz.

KEYWORDS

Advanced design system, Low noise amplifier, Radio-frequency, Noise figure, Wireless network, CMOS, RF switch, VLSI

Original Source Link : http://aircconline.com/vlsics/V3N2/3212vlsics14.pdf

http://airccse.org/journal/vlsi/vol3.html

A Detailed Survey on VLSI Architectures for Lifting based DWT for efficient hardware implementation

A Detailed Survey on VLSI Architectures for Lifting based DWT for efficient hardware implementation

Usha Bhanu.N1 and Dr.A.Chilambuchelvan2

1Research Scholar, Anna University, Chennai-25, INDIA

2Professor, R.M.D. Engineering college ,Chennai-601 206 , INDIA

Abstract

Evaluating the previous work is an important part of developing new hardware efficient methods for the implementation of DWT through Lifting schemes. The aim of this paper is to give a review of VLSI architectures for efficient hardware implementation of wavelet lifting schemes. The inherent in place computation of lifting scheme has many advantages over conventional convolution based DWT. The architectures are represented in terms of parallel filter, row column, folded, flipping and recursive structures. The methods for scanning of images are the line-based and the block-based and their characteristics for the given application are given. The various architectures are analyzed in terms of hardware and timing complexity involved with the given size of input image and required levels of decomposition. This study is useful for deriving an efficient method for improving the speed and hardware complexities of existing architectures and to design a new hardware implementation of multilevel DWT using lifting schemes.

Keywords

Discrete Wavelet Transform, Lifting schemes, VLSI architectures, image compression.

Original Source Link : http://aircconline.com/vlsics/V3N2/3212vlsics13.pdf

http://airccse.org/journal/vlsi/vol3.html

FAULT SECURE ENCODER AND DECODER WITH CLOCK GATING

FAULT SECURE ENCODER AND DECODER WITH CLOCK GATING

N.Kapileswar1 and P.Vijaya Santhi2

Dept.of ECE,NRI Engineering College, Pothavarapadu,INDIA

Abstract:

This paper presents circuit design for a low power fault secure encoder and decoder system. Memory cells in logic circuits have been protected from soft errors for more than a decade due to increase in soft error rates. In this paper the circuitry around the memory block have been susceptible to soft errors and must be protected from faults. The proposed design uses error correcting codes and ring counter addressing scheme. In the ring counter several new clock gating techniques are proposed to reduce power consumption. A fault secure Encoder and Decoder error free low power logic circuits can be achieved by the proposed design. Simulation results show great improvement in power consumption. Fault secure Encoder and Decoder with clock gated by CG-element consumes approximately half the power of that consumed by the fault free circuit which doesn’t employ clock gating technique 

Keywords:

GC-element, first-in–first-out (FIFO), gated-clock, ring-counter, Double edge triggered(DET ) D flipflop(DFF ), encoder, decoder, detector, corrector.

Original Source Link : http://aircconline.com/vlsics/V3N2/3212vlsics12.pdf

http://airccse.org/journal/vlsi/vol3.html

An approach to design Flash Analog to Digital Converter for High Speed and Low power Applications

An approach to design Flash Analog to Digital Converter for High Speed and Low power Applications

P.RAJESWARI1 . R.RAMESH2., A.R.ASHWATHA3.

1PhD scholar, Telecommunication Engg Dept, Dayanada Sagar College of Engineering,Bangalore, India.

2Professor, E&C Dept, Saveetha engineering college, Chennai, India.

3Professor & Head, TCE Dept, Dayanada Sagar College of Engineering, Bangalore,India. 

ABSTRACT

This paper proposes the Flash ADC design using Quantized Differential Comparator and fat tree encoder. This approach explores the use of a systematically incorporated input offset voltage in a differential amplifier for quantizing the reference voltages necessary for Flash ADC architectures, therefore eliminating the need for a passive resistor array for the purpose. This approach allows very small voltage comparison and complete elimination of resistor ladder circuit. The thermometer code-to-binary code encoder has become the bottleneck of the ultra-high speed flash ADCs. In this paper, the fat tree thermometer code to-binary code encoder is used for the ultra high speed flash ADCs. The simulation and the implementation results shows that the fat tree encoder performs the commonly used ROM encoder in terms of speed and power for the 6 bit CMOS flash ADC case. The speed is improved by almost a factor of 2 when using the fat tree encoder, which in fact demonstrates the fat tree encoder and it is an effective solution for the bottleneck problem in ultra-high speed ADCs.The design has been carried out for the 0.18um technology using CADENCE tool.

KEYWORDS

TIQ, FAT TREE TC-BC ENCODER, CMOS, ANALOG TO DIGITAL CONVERTER.

Original Source Link  : http://aircconline.com/vlsics/V3N2/3212vlsics11.pdf

http://airccse.org/journal/vlsi/vol3.html

WISHBONE BUS ARCHITECTURE – A SURVEY AND COMPARISON

WISHBONE BUS ARCHITECTURE – A SURVEY AND COMPARISON

Mohandeep Sharma1 and Dilip Kumar2

1Department of VLSI Design, Center for Development of Advanced Computing, Mohali, India

2ACS - Division, Center for Development of Advanced Computing, Mohali, India

ABSTRACT

The performance of an on-chip interconnection architecture used for communication between IP cores depends on the efficiency of its bus architecture. Any bus architecture having advantages of faster bus clock speed, extra data transfer cycle, improved bus width and throughput is highly desirable for a low cost, reduced time-to-market and efficient System-on-Chip (SoC). This paper presents a survey of WISHBONE bus architecture and its comparison with three other on-chip bus architectures viz. Advanced Microcontroller Bus Architecture (AMBA) by ARM, CoreConnect by IBM and Avalon by Altera. The WISHBONE Bus Architecture by Silicore Corporation appears to be gaining an upper edge over the other three bus architecture types because of its special performance parameters like the use of flexible arbitration scheme and additional data transfer cycle (Read-Modify-Write cycle). Moreover, its IP Cores are available free for use requiring neither any registration nor any agreement or license. 

KEYWORDS

SoC buses, WISHBONE Bus, WISHBONE Interface

Original Source Link : http://aircconline.com/vlsics/V3N2/3212vlsics10.pdf

http://airccse.org/journal/vlsi/vol3.html

FPGA Implementation of ADPLL with Ripple Reduction Techniques

FPGA Implementation of ADPLL with Ripple Reduction Techniques

Manoj Kumar1 and Kusum Lata2

Department of Electronics and Communication Engineering, Indian Institute of Information Technology, Allahabad, INDIA

ABSTRACT

In this paper FPGA implementation of ADPLL using Verilog is presented. ADPLL with ripple reduction techniques is also simulated and implemented on FPGA. For simulation ISE Xilinx 10.1 CAD is used.Vertex5 FPGA (Field Programmable Gate Array) is used for implementation. ADPLL performance improvement, while using ripple reduction techniques is also discussed. The ADPLL is designed at the central frequency of 100 kHz. The frequency range of ADPLL is 0 kHz to 199 kHz. But when it is implemented with ripple reduction techniques, the frequency range observed is from 11 kHz to 216 kHz.

KEYWORDS: 

DCO, ADPLL, LOOP FILTER, PHASE DETECTOR

Original sourece Link : http://aircconline.com/vlsics/V3N2/3212vlsics09.pdf

http://airccse.org/journal/vlsi/vol3.html

SCOPE OF REVERSIBLE ENGINEERING AT GATE-LEVEL: FAULT-TOLERANT COMBINATIONAL ADDERS

SCOPE OF REVERSIBLE ENGINEERING AT GATE-LEVEL: FAULT-TOLERANT COMBINATIONAL ADDERS

M.Bharathi 1, K.Neelima2

1Assistant Professor, ECE Department, Sree Vidyanikethan Engineering College(Autonomous),Tirupati-517102, India

2Assistant Professor, ECE Department, Sree Vidyanikethan Engineering College(Autonomous),Tirupati-517102, India.

Abstract

Reversible engineering has been one of the thrust areas ensuring that continual process of the innovation trends that explore and sustain the resources of the nature. This reversible engineering is used in many fields like quantum computing, low power CMOS design, nanotechnology, optical information processing, digital signal processing, cryptography, etc. These are the digital domain implementations of Reversible and Fault-Tolerant logic gates. Any arbitrary Boolean function can be synthesized by using the proposed parity preserving reversible gates. Not only the possibility of detecting errors is induced inherently in the proposed high speed adders at their output side but also it allows any fault that affects no more than a single signal that is detectable. The fault tolerant reversible full adder circuits are realized by using two IG gates only. The derived fault tolerant full adder is used for designing other arithmetic- logic circuit by using it as fundamental building block. The proposed reversible gate is designed to have less hardware complexity and efficiecyt in terms of gate count, garbage outputs and constant input. In this paper, we design BCD adder using carry select logic, Carry-select and Bypass adders using FG gates, and newly designed TG gates.

Keywords

Delay, Miniaturization, Reversibility 

Original Source Link : http://aircconline.com/vlsics/V3N2/3212vlsics08.pdf

http://airccse.org/journal/vlsi/vol3.html

A Low Power High Bandwidth Four Quadrant Analog Multiplier in 32 NM CNFET Technology

A Low Power High Bandwidth Four Quadrant Analog Multiplier in 32 NM CNFET Technology 

Ishit Makwana1 and Vitrag Sheth2

1Dept. of Electrical & Electronics Engg, Birla Institute of Technology & Science (BITS) Pilani, Pilani, India

2Hewlett Packard Global Soft India Pvt. Ltd., Bangalore, India

ABSTRACT

Carbon Nanotube Field Effect Transistor (CNFET) is a promising new technology that overcomes several limitations of traditional silicon integrated circuit technology. In recent years, the potential of CNFET for analog circuit applications has been explored. This paper proposes a novel four quadrant analog multiplier design using CNFETs. The simulation based on 32nm CNFET technology shows that the proposed multiplier has very low harmonic distortion (<0.45%), large input range (±400mV), large bandwidth (~50GHz) and low power consumption (~247µW), while operating at a supply voltage of ±0.9V.

KEYWORDS

Carbon Nanotube FET, Nanoelectronics, Analog Integrated Circuits, Analog Multipliers, Low Power.

Original Source Link : http://aircconline.com/vlsics/V3N2/3212vlsics07.pdf

http://airccse.org/journal/vlsi/vol3.html