MODELLING AND SIMULATION OF 128-BIT CROSSBAR SWITCH FOR NETWORK -ONCHIP
Mohammad Ayoub Khan1 and Abdul Quaiyum Ansari2
1Centre for Development of Advanced Computing,Ministry of Communications and Information Techology, Govt. of India, INDIA
2Department of Electrical Engineering, Jamia Millia Islamia, New Delhi, India
ABSTRACT
This is widely accepted that Network-on-Chip represents a promising solution for forthcoming complex embedded systems. The current SoC Solutions are built from heterogeneous hardware and Software components integrated around a complex communication infrastructure. The crossbar is a vital component of in any NoC router. In this work, we have designed a crossbar interconnect for serial bit data transfer and 128-parallel bit data transfer. We have shown comparision between power and delay for the serial bit and parallel bit data transfer through crossbar switch. The design is implemented in 0.180 micron TSM technology.The bit rate achived in serial transfer is slow as compared with parallel data transfer. The simulation resuls show that the critical path delay is less for parallel bit data transfer but power dissipation is high.
KEYWORDS
Network-on-Chip, routing, SoC, Crossbar
Original Source Link : http://aircconline.com/vlsics/V2N3/2311vlsics18.pdf
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