A NOVEL APPROACH TO MINIMIZE SPARE CELL LEAKAGE POWER CONSUMPTION DURING PHYSICAL DESIGN IMPLEMENTATION

A NOVEL APPROACH TO MINIMIZE SPARE CELL LEAKAGE POWER CONSUMPTION DURING PHYSICAL DESIGN IMPLEMENTATION

Vasantha Kumar B.V.P1, Dr. N. S. Murthy Sharma2, Dr. K. Lal Kishore3 and 4Jibanjeet Mishra

1Synopsys (India) Pvt. Ltd, Hyderabad, India.

2Principal, SV Institute of Engineering and Technology, Hyderabad, India.

3JNT University, ECE Dept, Hyderabad

4Synopsys (India) Pvt. Ltd, Hyderabad, India.

ABSTRACT

In IC designs leakage power constitutes significant amount power dissipation because CMOS gates are not perfect switches. The leakage power in CMOS gates is dependent on the states of the inputs. This leakage power will get dissipated even when the gates are in idle conditions. Traditionally ECO cells (or) spare cells remain idle in the design and thus contributes to significant state dependent leakage power consumption. In this paper we proposed novel solution to minimize the state dependent leakage power dissipation of the spare cells.

KEYWORDS

Engineering Change Order (ECO), ECO cell, Spare cell, State dependent, leakage power and switching probability

Original Source Link : http://aircconline.com/vlsics/V2N4/2411vlsics07.pdf

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