LINEARITY AND ANALOG PERFORMANCE ANALYSIS OF DOUBLE GATE TUNNEL FET: EFFECT OF TEMPERATURE AND GATE STACK
RAKHI NARANG1, MANOJ SAXENA2, R. S. GUPTA3 AND MRIDULA GUPTA1
1Semiconductor Device Research Laboratory, Department of Electronic Science,University of Delhi, South Campus, New Delhi, India
2Department of Electronics, Deen Dayal Upadhyaya College,University of Delhi, New Delhi, India
3Department of Electronics and Communication Engineering, Maharaja Agrasen Institute Of Technology, Sector-22, Rohini, Delhi, India
ABSTRACT
The linearity and analog performance of a Silicon Double Gate Tunnel Field Effect Transistor (DG-TFET) is investigated and the impact of elevated temperature on the device performance degradation has been studied. The impact on the device performance due to the rise in temperature and a gate stack (GS) architecture has also been investigated for the case of Silicon DG-MOSFET and a comparison with DGTFET is made. The parameters overning the analog performance and linearity have been studied, and high frequency simulations are carried out to determine the cut-off frequency of the device and its temperature dependence.
KEYWORDS
Analog, DG-TFET, Gate Stack, Linearity
Original Source Link : http://aircconline.com/vlsics/V2N3/2311vlsics16.pdf
No comments:
Post a Comment