DESIGN AND ASIC IMPLEMENTATION OF DUC/DDC FOR COMMUNICATION SYSTEMS

DESIGN AND ASIC IMPLEMENTATION OF DUC/DDC FOR COMMUNICATION SYSTEMS

Naagesh S. Bhat

Senior Product Engineer, Green Mil International Ltd., Bangalore, India

ABSTRACT

Communication systems use the concept of transmitting information using the electrical distribution network as a communication channel. To enable the transmission data signal modulated on a carrier signal is superimposed on the electrical wires. Typical power lines are designed to handle 50/60 Hz of AC power signal; however they can carry the signals up to 500 KHz frequency. This work aims to aid transmission/reception of an audio signal in the spectrum from 300 Hz to 4000 Hz using PLCC on a tunable carrier frequency in the spectrum from 200 KHz to 500 KHz. For digital amplitude modulation the sampling rate of the carrier and the audio signal has to be matched. Tunable carrier generation can be achieved with Direct Digital Synthesizers at a desired sampling rate. DSP Sample rate conversion techniques are very useful to make the sampling circuits to work on their own sampling rates which are fine for the data/modulated-carrier signal’s bandwidth. This also simplifies the complexity of the sampling circuits. Digital Up Conversion (DUC) and Digital Down Conversion (DDC) are DSP sample rate conversion techniques which refer to increasing and decreasing the sampling rate of a signal respectively. The objective was to design and implement low power ASIC of DUC and DDC designs at 65nm for PLCC. Low power implementation was carried out using Multi-VDD technique. MATLAB software models were used to understand the DUC and DDC designs. RTL to GDS flow was executed using Synopsys tools such as VCS, Design Compiler, IC Compiler and PrimeTime. Key milestones of this activity are RTL verification, synthesis, gate-level simulations, low power architecture definitions, physical implementation, ASIC signoff checks and postroute delay based simulations. Multi-VDD technique deployed on DUC and DDC helped to reduce the power consumption from 280.9uW to 198.07uW and from 176.26uW to 124.47uW respectively. DUC and DUC designs have met functionality at 64MHz clock frequency. Both the designs have passed postroute delay based simulations, static performance checks, power domain checks and TSMC’s 65nm design rule checks.

KEYWORDS

Power Line Carrier Communication, Digital Down-Counter, Digital Up-Counter, Application Specific Integrated Circuit, Multi-VDD, TSMC

Original Source Link : http://aircconline.com/vlsics/V2N4/2411vlsics10.pdf

http://airccse.org/journal/vlsi/vol2.html

AN EFFICIENT FPGA IMPLEMENTATION OF MRI IMAGE FILTERING AND TUMOUR CHARACTERIZATION USING XILINX SYSTEM GENERATOR

AN EFFICIENT FPGA IMPLEMENTATION OF MRI IMAGE FILTERING AND TUMOUR CHARACTERIZATION USING XILINX SYSTEM GENERATOR

Mrs. S. Allin Christe1, Mr.M.Vignesh2, Dr.A.Kandaswamy3

1,2Department of Electronics & Communication Engineering , PSG College of Technology, Coimbatore,India

3 Department of Biomedical Engineering, PSG College of Technology, Coimbatore,India

ABSTRACT

This paper presents an efficient architecture for various image filtering algorithms and tumor characterization using Xilinx System Generator (XSG). This architecture offers an alternative through a graphical user interface that combines MATLAB, Simulink and XSG and explores important aspectsconcerned to hardware implementation. Performance of this architecture implemented in SPARTAN-3E  Starter kit (XC3S500E-FG320) exceeds those of similar or greater resources architectures. The proposed architecture reduces the resources available on target device by 50%.

KEYWORDS

MRI, Matlab, Xilinx System Generator, FPGA, Edge Detection

Original Souce Link : http://aircconline.com/vlsics/V2N4/2411vlsics09.pdf

http://airccse.org/journal/vlsi/vol2.html

VLSI Design of Low Power High Speed 4 Bit Resolution Pipeline ADC In Submicron CMOS Technology

VLSI Design of Low Power High Speed 4 Bit Resolution Pipeline ADC In Submicron CMOS Technology

Ms. Rita M. Shende1 and Prof. Pritesh R. Gumble2

Department of Electronics & Telecommunication, Sipna’s College of Engineering & Technology Amravati, Maharashtra.

Department of Electronics & Telecommunications, Sipna’s College of Engineering & Technology Amravati, Maharashtra.

Abstract

Analog-to-digital converters (ADCs) are key design blocks and are currently adopted in many application fields to improve digital systems, which achieve superior performances with respect to analog solutions. Application such as wireless communication and digital audio and video have created the need for costeffective data converters that will achieve higher speed and resolution. Widespread usage confers great importance to the design activities, which nowadays largely contributes to the production cost in integrated circuit devices (ICs). Various examples of ADC applications can be found in data acquisition systems, measurement systems and digital communication systems also imaging, instrumentation systems. Since the ADC has a continuous, infinite –valued signal as its input, the important analog points on the transfer curve x-axis for an ADC are the ones that corresponding to changes in the digital output word. These input transitions determine the amount of INL and DNL associated with the converter. Hence, we have to considered all the parameters and improving the associated performance may significantly reduce the industrial cost of an ADC manufacturing process and improved the resolution and design specially power consumption . The paper presents a design of 4 bit Pipeline ADC with low power dissipation  mplemented in <0.18µm.

Keyword

ADC, PIPELINE, CMOS 

Original Source Link: http://aircconline.com/vlsics/V2N4/2411vlsics08.pdf

http://airccse.org/journal/vlsi/vol2.html

A NOVEL APPROACH TO MINIMIZE SPARE CELL LEAKAGE POWER CONSUMPTION DURING PHYSICAL DESIGN IMPLEMENTATION

A NOVEL APPROACH TO MINIMIZE SPARE CELL LEAKAGE POWER CONSUMPTION DURING PHYSICAL DESIGN IMPLEMENTATION

Vasantha Kumar B.V.P1, Dr. N. S. Murthy Sharma2, Dr. K. Lal Kishore3 and 4Jibanjeet Mishra

1Synopsys (India) Pvt. Ltd, Hyderabad, India.

2Principal, SV Institute of Engineering and Technology, Hyderabad, India.

3JNT University, ECE Dept, Hyderabad

4Synopsys (India) Pvt. Ltd, Hyderabad, India.

ABSTRACT

In IC designs leakage power constitutes significant amount power dissipation because CMOS gates are not perfect switches. The leakage power in CMOS gates is dependent on the states of the inputs. This leakage power will get dissipated even when the gates are in idle conditions. Traditionally ECO cells (or) spare cells remain idle in the design and thus contributes to significant state dependent leakage power consumption. In this paper we proposed novel solution to minimize the state dependent leakage power dissipation of the spare cells.

KEYWORDS

Engineering Change Order (ECO), ECO cell, Spare cell, State dependent, leakage power and switching probability

Original Source Link : http://aircconline.com/vlsics/V2N4/2411vlsics07.pdf

http://airccse.org/journal/vlsi/vol2.html

FAULT MODELING OF COMBINATIONAL AND SEQUENTIAL CIRCUITS AT REGISTER TRANSFER LEVEL

FAULT MODELING OF COMBINATIONAL AND SEQUENTIAL CIRCUITS AT REGISTER TRANSFER LEVEL

M.S.Suma1 and K.S.Gurumurthy2

1Department of Electronics and Communication Engineering, R.V.College of Engineering, Bangalore, India

2Department of Electronics and Communication Engineering, U.V.College of Engineering, Bangalore, India

ABSTRACT

As the complexity of Very Large Scale Integration (VLSI) is growing, testing becomes tedious and tougher. As of now fault models are used to test digital circuits at the gate level or below that level. By using fault models at the lower levels, testing becomes cumbersome and will lead to delays in the design cycle. In addition, developments in deep submicron technology provide an opening to new defects. We must develop efficient fault detection and location methods in order to reduce manufacturing costs and time to market. Thus there is a need to look for a new approach of testing the circuits at higher levels to speed up the design cycle. This paper proposes on Register Transfer Level (RTL) modeling for digital circuits and computing the fault coverage. The result obtained through this work establishes that the fault coverage with the RTL fault model is comparable to the gate level fault coverage.

KEYWORDS

Automatic test pattern generation (ATPG), fault coverage, fault simulation, stuck-at fault, RTL. 

Original Source Link : http://aircconline.com/vlsics/V2N4/2411vlsics06.pdf

http://airccse.org/journal/vlsi/vol2.html

Single bit full adder design using 8 transistors with novel 3 transistors XNOR gate

Single bit full adder design using 8 transistors with novel 3 transistors XNOR gate

Manoj Kumar1, Sandeep K. Arya1 and Sujata Pandey2

1Department of Electronics & Communication Engineering Guru Jambheshwar University of Science & Technology, Hisar, 125 001, India

2Amity University, Noida, 201303, India

Abstract:

In present work a new XNOR gate using three transistors has been presented, which shows power dissipation of 550.7272µW in 0.35µm technology with supply voltage of 3.3V. Minimum level for high output of 2.05V and maximum level for low output of 0.084V have been obtained. A single bit full adder using eight transistors has been designed using proposed XNOR cell, which shows power dissipation of 581.542µW. Minimum level for high output of 1.97V and maximum level for low output of 0.24V is obtained for sum output signal. For carry signal maximum level for low output of 0.32V and minimum level for high output of 3.2V have been achieved. Simulations have been performed by using SPICE based on TSMC 0.35µm CMOS technology. Power consumption of proposed XNOR gate and full adder has been compared with earlier reported circuits and proposed circuit’s shows better performance in terms of power consumption and transistor count.

Keywords:

 CMOS, exclusive-OR (XOR), exclusive-NOR (XNOR), full adder, low power, pass transistor logic. 

Original Source Link : http://aircconline.com/vlsics/V2N4/2411vlsics05.pdf

http://airccse.org/journal/vlsi/vol2.html

Design of Reversible Sequential Circuit Using Reversible Logic Synthesis

Design of Reversible Sequential Circuit Using Reversible Logic Synthesis

Md. Belayet Ali1, Md. Mosharof Hossin1 and Md. Eneyat Ullah1

1Department of Computer Science and Engineering Mawlana Bhashani Science and Technology University, Santosh, Tangail-1902,Bangladesh

Abstract

Reversible logic is one of the most vital issue at present time and it has different areas for its application, those are low power CMOS, quantum computing, nanotechnology, cryptography, optical computing, DNA computing, digital signal processing (DSP), quantum dot cellular automata, communication, computer graphics. It is not possible to realize quantum computing without implementation of reversible logic. The main purposes of designing reversible logic are to decrease quantum cost, depth of the circuits and the number of garbage outputs. In this paper, we have proposed a new reversible gate. And we have designed RS flip flop and D flip flop by using our proposed gate and Peres gate. The proposed designs are better than the existing proposed ones in terms of number of reversible gates and garbage outputs. So, this realization is more efficient and less costly than other realizations.

Keywords

Reversible logic, Reversible gate, Power dissipation, Flip-Flop, Garbage, BME gate. 

Original Source Link : http://aircconline.com/vlsics/V2N4/2411vlsics04.pdf

http://airccse.org/journal/vlsi/vol2.html

FPGA IMPLEMENTATION OF DEBLOCKING FILTER CUSTOM INSTRUCTION HARDWARE ON NIOS-II BASED SOC

FPGA IMPLEMENTATION OF DEBLOCKING FILTER CUSTOM INSTRUCTION HARDWARE ON NIOS-II BASED SOC

Bolla Leela Naresh1,  N.V.Narayana Rao 2 and Addanki Purna Ramesh3

Department of ECE, Sri Vasavi Engg College, Tadepalligudem, West Godavari (dt),Andhra Pradesh, India

ABSTRACT

This paper presents a frame work for hardware acceleration for post video processing system implemented on FPGA. The deblocking filter algorithms ported on SOC having Altera NIOS-II soft core processor.SOC designed with the help of SOPC builder .Custom instructions are chosen by identifying the most frequently used tasks in the algorithm and the instruction set of NIOS-II processor has been extended. Deblocking filter new instruction added to the processor that are implemented in hardware and interfaced to the NIOSII processor. New instruction added to the processor to boost the performance of the deblocking filter algorithm. Use of custom instructions the implemented tasks have been accelerated by 5.88%. The benefit of the speed is obtained at the cost of very small hardware resources.

KEYWORDS

Deblocking filter, SOC, NIOS-II soft processor, FPGA 

Original Source Link : http://aircconline.com/vlsics/V2N4/2411vlsics03.pdf

http://airccse.org/journal/vlsi/vol2.html

A NEW DESIGN TECHNIQUE OF REVERSIBLE BCD ADDER BASED ON NMOS WITH PASS TRANSISTOR GATES

A NEW DESIGN TECHNIQUE OF REVERSIBLE BCD ADDER BASED ON NMOS WITH PASS TRANSISTOR GATES

Md. Sazzad Hossain1, Md. Rashedul Hasan Rakib1, Md. Motiur Rahman1,A. S. M. Delowar Hossain1 and Md. Minul Hasan2

1Department of Computer Science and Engineering, Mawlana Bhashani Science & Technology University, Santosh, Tangail-1902, Bangladesh

2Amader Ltd, 5B Union Erin, 9/1 North Dhanmondi, Kalabagan, Dhaka, Bangladesh.

ABSTRACT

In this paper, we have proposed a new design technique of BCD Adder using newly constructed reversible gates are based on NMOS with pass transistor gates, where the conventional reversible gates are based on CMOS with transmission gates. We also compare the proposed reversible gates with the conventional CMOS reversible gates which show that the required number of Transistors is significantly reduced.

KEYWORDS

CMOS, Feynman gates, Fredkin gate, NMOS & pass transistor. 

Original Source Link : http://aircconline.com/vlsics/V2N4/2411vlsics02.pdf

http://airccse.org/journal/vlsi/vol2.html

A NEW FULL ADDER CELL FOR MOLECULAR ELECTRONICS

A NEW FULL ADDER CELL FOR MOLECULAR ELECTRONICS

Mehdi Ghasemi1,2, Mohammad Hossein Moaiyeri1,2, and Keivan Navi1,2

1Faculty of Electrical and Computer Engineering, Shahid Beheshti University G.C.,Tehran, Iran.

2Nanotechnology and Quantum Computing Lab, Shahid Beheshti University G.C.,Tehran, Iran.

ABSTRACT

Due to high power consumption and difficulties with minimizing the CMOS transistor size, molecular electronics has been introduced as an emerging technology. Further, there have been noticeable advances in fabrication of molecular wires and switches and also molecular diodes can be used for designing different logic circuits. Considering this novel technology, we use molecules as the active components of the circuit, for transporting electric charge. In this paper, a full adder cell based on molecular electronics is presented. This full adder is consisted of resonant tunneling diodes and transistors which are implemented via molecular electronics. The area occupied by this kind of full adder would be much times smaller than the conventional designs and it can be used as the building block of more complex molecular arithmetic circuits.

KEYWORDS

Logic circuits, full adder, nanotechnology, molecular electronics, resonant tunneling diode (RTD)

Original Source Link : http://aircconline.com/vlsics/V2N4/2411vlsics01.pdf

http://airccse.org/journal/vlsi/vol2.html

Reducing power in using different technologies using FSM architecture

Reducing power in using different technologies using FSM architecture

Himani Mittal, Dinesh Chandra2, Sampath Kumar3

1,2,3J.S.S.Academy of Technical Education ,NOIDA,U.P,INDIA

Abstract:

As in today’s date fuel consumption is important in everything from scooters to oil tankers, power consumption is a key parameter in most electronics applications. The most obvious applications for which power consumption is critical are battery-powered applications, such as home thermostats and security systems, in which the battery must last for years. Low power also leads to smaller power supplies, less expensive batteries, and enables products to be powered by signal lines (such as fire alarm wires) lowering the cost of the end-product. As a result, low power consumption has become a key parameter of microcontroller designs . The purpose of this paper is to summarize, mainly by way of examples,what in our experience are the most trustful approaches to lowpower design. In other words, our contribution should not be intended as an exhaustive survey of the existing literature on low-power esign; rather, we would like to provide insights a designer can rely upon when power consumption is a critical constraint.We will focus on the reduction of power consumption on different technologies for different values of oicapacitance and also compare power saving in technologies.

Keywords:

FSM Decomposition [2] ,Mealy and Moore Machines , Capacitance[5], Power saving

Original Source Link : http://aircconline.com/vlsics/V2N3/2311vlsics20.pdf

http://airccse.org/journal/vlsi/vol2.html

Impact of Interface Fixed Charges on the Performance of the Channel Material Engineered Cylindrical Nanowire MOSFET

Impact of Interface Fixed Charges on the Performance of the Channel Material Engineered Cylindrical Nanowire MOSFET

Rajni Gautam1, Manoj Saxena2, R.S.Gupta3 and Mridula Gupta1

1Semiconductor Device Research Laboratory, Department Of Electronic Science,University Of Delhi, India

2Department Of Electronics, Deen Dayal Upadhyaya college,University Of Delhi, India

3 Department Of Electronics and communication Engineering, Maharaja Agrasen Institute Of Technology, India

ABSTRACT

The paper presents a simulation study of effect of interface fixed charges on the performance of the cylindrical nanowire MOSFET for different channel materials (Si, GaAs and Ge). The objective of the present work is to study the effect of hot carrier damage/stress induced damage/process damage/radiation damage induced fixed charges at the semiconductor-oxide interface of the cylindrical nanowire MOSFET. Also the circuit reliability issues of the device are discussed in terms of the performance degradation due to interface fixed charges. The performance has been compared for the three materials in terms of drain current driving capability, Ion/Ioff ratio, early voltage, transconductance, parasitic gate capacitance, intrinsic delay, current gain and power gain of the device.

KEYWORDS

ATLAS-3D, channel length modulation, fixed Charges, hot carrier effect, interface traps, nanowire MOSFET. 

Original Source Link : http://aircconline.com/vlsics/V2N3/2311vlsics19.pdf

http://airccse.org/journal/vlsi/vol2.html

MODELLING AND SIMULATION OF 128-BIT CROSSBAR SWITCH FOR NETWORK -ONCHIP

MODELLING AND SIMULATION OF 128-BIT CROSSBAR SWITCH FOR NETWORK -ONCHIP

Mohammad Ayoub Khan1 and Abdul Quaiyum Ansari2

1Centre for Development of Advanced Computing,Ministry of Communications and Information Techology, Govt. of India, INDIA

2Department of Electrical Engineering, Jamia Millia Islamia, New Delhi, India

ABSTRACT

This is widely accepted that Network-on-Chip represents a promising solution for forthcoming complex embedded systems. The current SoC Solutions are built from heterogeneous hardware and Software components integrated around a complex communication infrastructure. The crossbar is a vital component of in any NoC router. In this work, we have designed a crossbar interconnect for serial bit data transfer and 128-parallel bit data transfer. We have shown comparision between power and delay for the serial bit and parallel bit data transfer through crossbar switch. The design is implemented in 0.180 micron TSM technology.The bit rate achived in serial transfer is slow as compared with parallel data transfer. The simulation resuls show that the critical path delay is less for parallel bit data transfer but power dissipation is high.

KEYWORDS

Network-on-Chip, routing, SoC, Crossbar

Original Source Link : http://aircconline.com/vlsics/V2N3/2311vlsics18.pdf

http://airccse.org/journal/vlsi/vol2.html

Braun’s Multiplier Implementation using FPGA with Bypassing Techniques.

Braun’s Multiplier Implementation using FPGA with Bypassing Techniques.

Anitha R1, Bagyaveereswaran V2

1&2 VIT University, Vellore, India.

Abstract:

The developing an Application Specific Integrated Circuits (ASICs) will cost very high, the circuits should be proved and then it would be optimized before implementation. Multiplication which is the basic building block for several DSP processors, Image processing and many other. The Braun multipliers can easily be implemented using Field Programmable Gate Array (FPGA) devices. This research presented the comparative study of Spartan-3E, Virtex-4, Virtex-5 and Virtex-6 Low Power FPGA devices. The implementation of Braun multipliers and its bypassing techniques is done using Verilog HDL. We are proposing that adder block which we implemented our design (fast addition) and we compared the results of that so that our proposed method is effective when compare to the conventional design. There is the reduction in the resources like delay LUTs, number of slices used. Results are showed and it is verified using the Spartan-3E, Virtex-4 and Virtex-5 devices. The Virtex-5 FPGA has shown the good performance as compared to Spartan-3E and Virtex-4 FPGA devices.

Key words:

Digital Signal Processing (DSP), Field Programmable Gate Array (FPGA), fast addition, Spartan-3E, truncated multiplier, Verilog HDL, Virtex-4, Virtex-5, Virtex – 6 Low power. 

Original Scource Link : http://aircconline.com/vlsics/V2N3/2311vlsics17.pdf

http://airccse.org/journal/vlsi/vol2.html

LINEARITY AND ANALOG PERFORMANCE ANALYSIS OF DOUBLE GATE TUNNEL FET: EFFECT OF TEMPERATURE AND GATE STACK

LINEARITY AND ANALOG PERFORMANCE ANALYSIS OF DOUBLE GATE TUNNEL FET: EFFECT OF TEMPERATURE AND GATE STACK

RAKHI NARANG1, MANOJ SAXENA2, R. S. GUPTA3 AND MRIDULA GUPTA1

1Semiconductor Device Research Laboratory, Department of Electronic Science,University of Delhi, South Campus, New Delhi, India

2Department of Electronics, Deen Dayal Upadhyaya College,University of Delhi, New Delhi, India

3Department of Electronics and Communication Engineering, Maharaja Agrasen Institute Of Technology, Sector-22, Rohini, Delhi, India

ABSTRACT

The linearity and analog performance of a Silicon Double Gate Tunnel Field Effect Transistor (DG-TFET) is investigated and the impact of elevated temperature on the device performance degradation has been studied. The impact on the device performance due to the rise in temperature and a gate stack (GS) architecture has also been investigated for the case of Silicon DG-MOSFET and a comparison with DGTFET is made. The parameters overning the analog performance and linearity have been studied, and high frequency simulations are carried out to determine the cut-off frequency of the device and its temperature dependence.

KEYWORDS

 Analog, DG-TFET, Gate Stack, Linearity

Original Source Link : http://aircconline.com/vlsics/V2N3/2311vlsics16.pdf

http://airccse.org/journal/vlsi/vol2.html

POWER AWARE PHYSICAL MODEL FOR 3D IC’S

POWER AWARE PHYSICAL MODEL FOR 3D IC’S

Yasmeen Hasan

Dept Of ECE, Integral University, Lucknow,India 

Abstract:

 In this work we have proposed a geometric model that is employed to devise a scheme for identifying the hotspots and zones in a chip. These spots or zone need to be guarded thermally to ensure performance and reliability of the chip. The model namely continuous unit sphere model has been presented taking into account that the 3D region of the chip is uniform, thereby reflecting on the possible locations of heat sources and the target observation points. The experimental results for the – continuous domain establish that a region which does not contain any heat sources may become hotter than the regions containing the thermal sources. Thus a hotspot may appear away from the active sources, and placing heat sinks on the active thermal sources alone may not suffice to tackle thermal imbalance. Power management techniques aid in obtaining a uniform power profile throughout the chip, but we propose an algorithm using minimum bipartite matching where we try to move the sources minimally (with minimum perturbation in the chip floor plan) near cooler points (blocks) to obtain a uniform power profile due to diffusion of heat from hotter point to cooler ones.

Keywords :

3D chips, Hotspots ,Floorplaning ,Continuous domain, Integrated circuits, Power management ,Target point , Source point, Heat sink,Coarse mesh(CM),Fine mesh(FM), Effective thermal conductivity,etc 

Original Source Link : http://aircconline.com/vlsics/V2N3/2311vlsics15.pdf

http://airccse.org/journal/vlsi/vol2.html

PERFORMANCE EVALUATION OF LOW POWER CARRY SAVE ADDER FOR VLSI APPLICATIONS

PERFORMANCE EVALUATION OF LOW POWER CARRY SAVE ADDER FOR VLSI APPLICATIONS

Divya Tripathi and Subodh Wairya

Department of Electronics Engineering, Institute of Engineering & Technology, Lucknow

ABSTRACT

This report examines the subject of sub threshold leakage on carry save adder. When the gate to source voltage reduces to the threshold voltage at that place is yet some amount of current flow in the circuit and that is undesired. As the process technology advancing much rapidly the threshold voltage of MOS devices reduces very drastically, and it must be applied in lower power devices since it contributes to low amount of leakage current which confine increases the power consumption of the devices. Adders are the basic building blocks for any digital circuit design and used in almost all arithmetic’s. The CSA proves efficient adders due to its quick and precise computations. Hence this paper performs sub threshold analysis on CSA and the scrutinize results that the total average power is around 4.93µW, the propagation delay for complete operation is 16.3ns and since this design uses GDI cell so there is a reduction in area with 37%.

.

KEYWORDS

Sub threshold Leakage, Gate Diffusion Input (GDI), Carry Save Adder (CSA), Leakage current, Transistor Modeling.

Original Source Link : http://aircconline.com/vlsics/V9N3/9318vlsi05.pdf

http://airccse.org/journal/vlsi/current.html

COVERAGE DRIVEN FUNCTIONAL TESTING ARCHITECTURE FOR PROTOTYPING SYSTEM USING SYNTHESIZABLE ACTIVE AGENT

COVERAGE DRIVEN FUNCTIONAL TESTING ARCHITECTURE FOR PROTOTYPING SYSTEM USING SYNTHESIZABLE ACTIVE AGENT

Dipakkumar Modi and Usha Mehta

EC Department, Institute of Technology, Nirma University, Ahmedabad, India

ABSTRACT

Time and efforts for functional testing of digital logic is big chunk of overall project cycle in VLSI industry. Progress of functional testing is measured by functional coverage where test-plan defines what needs to be covered, and test-results indicates quality of stimulus. Claiming closer of functional testing requires that functional coverage hits 100% of original test-plan. Depending on the complexity of the design, availability of resources and budget, various methods are used for functional testing. Software simulations using various logic simulators, available from Electronic Design Automation (EDA) companies, is primary method for functional testing. The next level in functional testing is pre-silicon verification  using Field Programmable Gate Array (FPGA) prototype and/or emulation platforms for stress testing the Design Under Test (DUT). With all the efforts, the purpose is to gain confidence on maturity of DUT to ensuresfirst time silicon success that meets time to market needs of the industry. For any test-environment the bottleneck, in achieving verification closer, is controllability and observability that is quality of stimulus to unearth issues at early stage and coverage calculation. Software simulation, FPGA prototype, or emulation, each method has its own limitations, be it test-time, ease of use, or cost of software, tools and hardware-platform. Compared to software simulation, FPGA prototyping and emulation methods pose greater challenges in quality stimulus generation and coverage calculation. Many researchers have identified the problems of bug-detection / localization, but very few have touched the concept of quality stimulus generation that leads to better functional coverage and thereby uncover hidden bugs in FPGA prototype verification setup. This paper presents a novel approach to address above-mentioned issues by embedding synthesizable active-agent and coverage collector into FPGA prototype. The proposed  architecture has been experimented for functional and stress testing of Universal Serial Bus (USB) Link Training and Status State Machine (LTSSM) logic module as DUT in FPGA prototype. The proposed solution is fully synthesizable and hence can be used in both software simulation as well as in prototype system. The biggest advantage is plug and play nature of this active-agent component, that allows its reusability in any USB3.0 LTSSM digital core.

KEYWORDS

Testing, Functional Coverage, Synthesizable Active Agent, Universal Serial Bus (USB), Link Training and Status State Machine (LTSSM)

Original Source Link : http://aircconline.com/vlsics/V9N3/9318vlsi04.pdf

http://airccse.org/journal/vlsi/current.html

VERIFICATION OF DRIVER LOGIC USING AMBAAXI UVM

VERIFICATION OF DRIVER LOGIC USING AMBAAXI UVM

Bijal Thakkar1 and V Jayashree2

1Department of Electronics Engineering, D.K.T.E, Ichalkaranji, Maharashtra,India

2 D.K.T.E.Ichalkaranji,Shivaji University,Kolhapur,Maharashtra, India

ABSTRACT

Advanced Extensible Interface (AXI) is the most commonly used bus protocols in the day-to-day because of its high performance and high-frequency operation without using complex bridges. AXI is also backward compatible with existing AHB and APB interfaces. So verification of driver logic using AMBA-AXI UVM is presented in this paper. The AXI is used for multiple outstanding operations which is only possible in the other protocol but it is possible in AXI because it contains different write address and data channels and AXI also supports out of order transfer based on the transaction ID which is generated at the start of the transfer. The driver logic for the AXI has been designed and implemented using the Universal Verification Methodology (UVM).The signaling of the five channels such as write address, write data, write response, read address, read data channel of AXI protocol are considered for verification. According to the AXI protocol,the signals of these channels are driven to the interconnect and results are observed for single master and single slave. The driver logic has been implemented and verified successfully according to AXI protocol using the Rivera Pro. The results observed for single master and single slave have shown the correctness of AMBA-AXI design in Verilog.

KEYWORDS

AMBA(Advance Microcontroller Bus Architecture),AXI(Advanced Extensible Interface),UVM(Universal Verification Methodology),channel. 

Original Source Link : http://aircconline.com/vlsics/V9N3/9318vlsi03.pdf

http://airccse.org/journal/vlsi/current.html

VLSI DESIGN OF AMBA BASED AHB2APBBRIDGE

VLSI DESIGN OF AMBA BASED AHB2APBBRIDGE

Aparna Kharade1 and V. Jayashree2

1Department of Electronics, D.K.T.E. Ichalkaranji, Maharashtra, India

2 D.K.T.E.Ichalkaranji, Shivaji University, Kolhapur, Maharashtra, India

ABSTRACT

The Advanced Microcontroller Bus Architecture (AMBA) is an open System-on-Chip bus protocol for highperformance buses to communicate with low-power devices. In the AMBA Advanced High Performance bus (AHB) a system bus is used to connect a processor, a DSP, and high-performance memory controllers where as the AMBA Advanced Peripheral Bus (APB) is used to connect (Universal Asynchronous Receiver Transmitter) UART. It also contains a Bridge, which connects the AHB and APB buses. Bridges are standard bus-to-bus interfaces that allow IPs connected to different buses to communicate with each other in a standardized way. So AHB2APB bridge is designed, implemented using VERILOG tool and tested using Verilog testbench and is reported in this paper. A synthesizable RTL code of a complex interface bridge between AHB and APB is developed and known as AHB2APB Bridge. The simulated AHB2APB Bridge results are promising and can be further tested for its verstality by writing a verification program using UVM in future.

KEYWORDS

AMBA; AHB2APB; SOC; VERILOG; XILINX; 

Original Source Link : http://aircconline.com/vlsics/V9N3/9318vlsi02.pdf

http://airccse.org/journal/vlsi/current.html

IMPLEMENTATION OF LOW POWER ADIABATIC SRAM

IMPLEMENTATION OF LOW POWER ADIABATIC SRAM

Savitha S M1, Rajani2 and Shivaling M Hunagund3

1Department of Electronics and Communication, Visvesvaraya Technological University,Belagavi, Karnataka

2HOD of Department of Telecommunication, Visvesvaraya Technological University,Belagavi, Karnataka

3Asst Prof. of Department of Electronics and Communication, Visvesvaraya Technological University,Belagavi, Karnataka

ABSTRACT

 In the featuring VLSI era, compact electronic devices are popular. The reliability and durability of such compact devices relies on low power utilization. The purpose of this project was to implement a low power adiabatic Static Random Access Memory (SRAM), with the following objectives - To reduce the power waste by means of stepwise charging using tank capacitors which is an adiabatic way of generating power clock. This method is capable of recuperating the electrical energy back to the source. Further to examine the Static Noise Margin (SNM) – a parameter which gives detailed information about the cell stability – in contrast with conventional 6T, 7T and 8T topologies of SRAM under 180 nm technology. Finally, SNM variations with respect to process parameters are also discussed. All the implementations and analysis were made using CADENCE tool and MATLAB tool.

KEYWORDS

SRAM, Adiabatic, CMOS, Stepwise Charging, SNM and Process variations. 

Original Source Link : http://aircconline.com/vlsics/V9N3/9318vlsi01.pdf

http://airccse.org/journal/vlsi/current.html

Current Issue

Current Issue

June 2018, Volume 9, Number 3

Implementation of Low Power Adiabatic SRAM
http://aircconline.com/vlsics/V9N3/9318vlsi01.pdf

VLSI Design of AMBA Based AHB2APB Bridge
http://aircconline.com/vlsics/V9N3/9318vlsi02.pdf

Verification of Driver Logic Using AMBA-AXI UVM
http://aircconline.com/vlsics/V9N3/9318vlsi03.pdf

Coverage Driven Functional Testing Architecture for Prototyping System Using Synthesizable Active Agent
http://aircconline.com/vlsics/V9N3/9318vlsi04.pdf

Performance Evaluation of Low Power Carry Save Adder for VLSI Applications
http://aircconline.com/vlsics/V9N3/9318vlsi05.pdf