An approach to design Flash Analog to Digital Converter for High Speed and Low power Applications

An approach to design Flash Analog to Digital Converter for High Speed and Low power Applications

P.RAJESWARI1 . R.RAMESH2., A.R.ASHWATHA3.

1PhD scholar, Telecommunication Engg Dept, Dayanada Sagar College of Engineering,Bangalore, India.

2Professor, E&C Dept, Saveetha engineering college, Chennai, India.

3Professor & Head, TCE Dept, Dayanada Sagar College of Engineering, Bangalore,India. 

ABSTRACT

This paper proposes the Flash ADC design using Quantized Differential Comparator and fat tree encoder. This approach explores the use of a systematically incorporated input offset voltage in a differential amplifier for quantizing the reference voltages necessary for Flash ADC architectures, therefore eliminating the need for a passive resistor array for the purpose. This approach allows very small voltage comparison and complete elimination of resistor ladder circuit. The thermometer code-to-binary code encoder has become the bottleneck of the ultra-high speed flash ADCs. In this paper, the fat tree thermometer code to-binary code encoder is used for the ultra high speed flash ADCs. The simulation and the implementation results shows that the fat tree encoder performs the commonly used ROM encoder in terms of speed and power for the 6 bit CMOS flash ADC case. The speed is improved by almost a factor of 2 when using the fat tree encoder, which in fact demonstrates the fat tree encoder and it is an effective solution for the bottleneck problem in ultra-high speed ADCs.The design has been carried out for the 0.18um technology using CADENCE tool.

KEYWORDS

TIQ, FAT TREE TC-BC ENCODER, CMOS, ANALOG TO DIGITAL CONVERTER.

Original Source Link  : http://aircconline.com/vlsics/V3N2/3212vlsics11.pdf

http://airccse.org/journal/vlsi/vol3.html

WISHBONE BUS ARCHITECTURE – A SURVEY AND COMPARISON

WISHBONE BUS ARCHITECTURE – A SURVEY AND COMPARISON

Mohandeep Sharma1 and Dilip Kumar2

1Department of VLSI Design, Center for Development of Advanced Computing, Mohali, India

2ACS - Division, Center for Development of Advanced Computing, Mohali, India

ABSTRACT

The performance of an on-chip interconnection architecture used for communication between IP cores depends on the efficiency of its bus architecture. Any bus architecture having advantages of faster bus clock speed, extra data transfer cycle, improved bus width and throughput is highly desirable for a low cost, reduced time-to-market and efficient System-on-Chip (SoC). This paper presents a survey of WISHBONE bus architecture and its comparison with three other on-chip bus architectures viz. Advanced Microcontroller Bus Architecture (AMBA) by ARM, CoreConnect by IBM and Avalon by Altera. The WISHBONE Bus Architecture by Silicore Corporation appears to be gaining an upper edge over the other three bus architecture types because of its special performance parameters like the use of flexible arbitration scheme and additional data transfer cycle (Read-Modify-Write cycle). Moreover, its IP Cores are available free for use requiring neither any registration nor any agreement or license. 

KEYWORDS

SoC buses, WISHBONE Bus, WISHBONE Interface

Original Source Link : http://aircconline.com/vlsics/V3N2/3212vlsics10.pdf

http://airccse.org/journal/vlsi/vol3.html

FPGA Implementation of ADPLL with Ripple Reduction Techniques

FPGA Implementation of ADPLL with Ripple Reduction Techniques

Manoj Kumar1 and Kusum Lata2

Department of Electronics and Communication Engineering, Indian Institute of Information Technology, Allahabad, INDIA

ABSTRACT

In this paper FPGA implementation of ADPLL using Verilog is presented. ADPLL with ripple reduction techniques is also simulated and implemented on FPGA. For simulation ISE Xilinx 10.1 CAD is used.Vertex5 FPGA (Field Programmable Gate Array) is used for implementation. ADPLL performance improvement, while using ripple reduction techniques is also discussed. The ADPLL is designed at the central frequency of 100 kHz. The frequency range of ADPLL is 0 kHz to 199 kHz. But when it is implemented with ripple reduction techniques, the frequency range observed is from 11 kHz to 216 kHz.

KEYWORDS: 

DCO, ADPLL, LOOP FILTER, PHASE DETECTOR

Original sourece Link : http://aircconline.com/vlsics/V3N2/3212vlsics09.pdf

http://airccse.org/journal/vlsi/vol3.html

SCOPE OF REVERSIBLE ENGINEERING AT GATE-LEVEL: FAULT-TOLERANT COMBINATIONAL ADDERS

SCOPE OF REVERSIBLE ENGINEERING AT GATE-LEVEL: FAULT-TOLERANT COMBINATIONAL ADDERS

M.Bharathi 1, K.Neelima2

1Assistant Professor, ECE Department, Sree Vidyanikethan Engineering College(Autonomous),Tirupati-517102, India

2Assistant Professor, ECE Department, Sree Vidyanikethan Engineering College(Autonomous),Tirupati-517102, India.

Abstract

Reversible engineering has been one of the thrust areas ensuring that continual process of the innovation trends that explore and sustain the resources of the nature. This reversible engineering is used in many fields like quantum computing, low power CMOS design, nanotechnology, optical information processing, digital signal processing, cryptography, etc. These are the digital domain implementations of Reversible and Fault-Tolerant logic gates. Any arbitrary Boolean function can be synthesized by using the proposed parity preserving reversible gates. Not only the possibility of detecting errors is induced inherently in the proposed high speed adders at their output side but also it allows any fault that affects no more than a single signal that is detectable. The fault tolerant reversible full adder circuits are realized by using two IG gates only. The derived fault tolerant full adder is used for designing other arithmetic- logic circuit by using it as fundamental building block. The proposed reversible gate is designed to have less hardware complexity and efficiecyt in terms of gate count, garbage outputs and constant input. In this paper, we design BCD adder using carry select logic, Carry-select and Bypass adders using FG gates, and newly designed TG gates.

Keywords

Delay, Miniaturization, Reversibility 

Original Source Link : http://aircconline.com/vlsics/V3N2/3212vlsics08.pdf

http://airccse.org/journal/vlsi/vol3.html

A Low Power High Bandwidth Four Quadrant Analog Multiplier in 32 NM CNFET Technology

A Low Power High Bandwidth Four Quadrant Analog Multiplier in 32 NM CNFET Technology 

Ishit Makwana1 and Vitrag Sheth2

1Dept. of Electrical & Electronics Engg, Birla Institute of Technology & Science (BITS) Pilani, Pilani, India

2Hewlett Packard Global Soft India Pvt. Ltd., Bangalore, India

ABSTRACT

Carbon Nanotube Field Effect Transistor (CNFET) is a promising new technology that overcomes several limitations of traditional silicon integrated circuit technology. In recent years, the potential of CNFET for analog circuit applications has been explored. This paper proposes a novel four quadrant analog multiplier design using CNFETs. The simulation based on 32nm CNFET technology shows that the proposed multiplier has very low harmonic distortion (<0.45%), large input range (±400mV), large bandwidth (~50GHz) and low power consumption (~247µW), while operating at a supply voltage of ±0.9V.

KEYWORDS

Carbon Nanotube FET, Nanoelectronics, Analog Integrated Circuits, Analog Multipliers, Low Power.

Original Source Link : http://aircconline.com/vlsics/V3N2/3212vlsics07.pdf

http://airccse.org/journal/vlsi/vol3.html

HIGH SPEED CONTINUOUS-TIME BANDPASS Σ∆ ADC FOR MIXED SIGNAL VLSI CHIPS

HIGH SPEED CONTINUOUS-TIME BANDPASS Σ∆ ADC FOR MIXED SIGNAL VLSI CHIPS

P.A.HarshaVardhini1 and Dr.M.MadhaviLatha2

1Ph.D Scholar, Dept. of ECE, J.N.T.U, Hyderabad, A.P, India.

2Professor and Head, Dept. of ECE, J.N.T.U, Hyderabad, A.P, India.

ABSTRACT

With the unremitting progress in VLSI technology, there is a commensurate increase in performance demand on analog to digital converter and are now being applied to wideband communication systems. sigma Delta (Σ∆) converter is a popular technique for obtaining high resolution with relatively small bandwidth. Σ∆ ADCs which trade sampling speed for resolution can benefit from the speed advantages of nm-CMOS technologies. This paper compares various Band pass sigma Delta ADC architectures, both continuous-time and discrete-time, in respect of power consumption and SNDR. Design of 2nd order multibit continuous time band pass Σ∆ modulator is discussed with the methods to resolve DAC non-idealities.

KEYWORDS

CMOS, Over sampling, Noise shaping, Sigma Delta Modulation, Bandpass Σ∆ modulator, Dynamic element matching, Data weighted averaging

Original Source Link : http://aircconline.com/vlsics/V3N2/3212vlsics06.pdf

http://airccse.org/journal/vlsi/vol3.html

Microcontroller Based Testing of Digital IP-Core

Microcontroller Based Testing of Digital IP-Core

Amandeep Singh1 and Balwinder Singh2

1-2Acadmic and Consultancy Services Division, Centre for Development of Advanced Computing(C-DAC), Mohali, India

ABSTRACT

Testing core based System on Chip [1] is a challenge for the test engineers. To test the complete SOC at one time with maximum fault coverage, test engineers prefer to test each IP-core separately. At speed testing using external testers is more expensive because of gigahertz processor. The purpose of this paper is to develop cost efficient and flexible test methodology for testing digital IP-cores [2]. The prominent feature of the approach is to use microcontroller to test IP-core. The novel feature is that there is no need of test pattern generator and output response analyzer as microcontroller performs the function of both. This approach has various advantages such as at speed testing, low cost, less area overhead and greater flexibility since most of the testing process is based on software.

KEYWORDS

Microcontroller, FPGA, Testing, TMR, SOC

Original Source Link : http://aircconline.com/vlsics/V3N2/3212vlsics05.pdf

http://airccse.org/journal/vlsi/vol3.html