MODELING OF BUILT-IN POTENTIAL VARIATIONS OF CYLINDRICAL SURROUNDING GATE (CSG) MOSFETS

MODELING OF BUILT-IN POTENTIAL VARIATIONS OF CYLINDRICAL SURROUNDING GATE (CSG) MOSFETS

Santosh Kumar Gupta1 and S. Baishya2

Department of Electronics & Communication Engineering, National Institute of Technology Silchar, Assam – 788 010, INDIA

ABSTRACT

Due to aggressive scaling of MOSFETs the parasitic fringing field plays a major role in deciding its characteristics. These fringing fields are now not negligible and should be taken into account for deriving the MOSFET models. Due to this fringing field effect there are some charges induced in the source/drain extension regions which will change the potential barrier at the source-channel from its theoretical nominal values. In this paper an attempt has been made to model variation of built-in potential variation for a cylindrical surrounding gate MOSFET. The model has been verified to be working in good agreement with the variations of gate length and channel radius.

KEYWORDS

Barrier lowering, cylindrical surround gate (CSG) MOSFET, fringing field, short channel effects (SCEs) 

Original Source Link : http://aircconline.com/vlsics/V3N5/3512vlsics06.pdf

http://airccse.org/journal/vlsi/vol3.html

LOW POWER DYNAMIC BUFFER CIRCUITS

LOW POWER DYNAMIC BUFFER CIRCUITS

Amit Kumar Pandey, Ram Awadh Mishra and Rajendra Kumar Nagaria

Department of Electronics and Communication, M.N.N.I.T, Allahabad, India

ABSTRACT

In this paper we propose two buffer circuits for footed domino logic circuit. It minimizes redundant  switching at the output node. These circuits prevent propagation of precharge pulse to the output node during precharge phase which saves power consumption. Simulation is done using 0.18µm CMOS technology. We have calculated the power consumption, delay and power delay product of proposed circuits and compared the results with existing standard domino circuit for different logic function, loading condition, clock frequency, temperature and power supply. Our proposed circuits reduce power consumption and power delay product as compared to standard domino circuit.

KEYWORDS

Buffer, Dynamic circuit, Power consumption, Delay, Precharge pulse. 

Original Source Link : http://aircconline.com/vlsics/V3N5/3512vlsics05.pdf

http://airccse.org/journal/vlsi/vol3.html

DBR: A Simple, Fast and Efficient Dynamic Network Reconfiguration Mechanism Based on Deadlock Recovery Scheme

DBR: A Simple, Fast and Efficient Dynamic Network Reconfiguration Mechanism Based on Deadlock Recovery Scheme

Majed ValadBeigi, Farshad Safaei and Bahareh Pourshirazi

Department of Electrical and Computer Engineering, Shahid Beheshti University G.C, Evin 1983963113, Tehran, IRAN

ABSTRACT

Dynamic network reconfiguration is described as the process of replacing one routing function with another while the network keeps running. The main challenge is avoiding deadlock anomalies while keeping limitations on message injection and forwarding minimal. Current approaches, whose complexity is so high that their practical applicability is limited, either require the existence of extra network resources like virtual channels, or they affect the performance of the network during the reconfiguration process. In this paper we present a simple, fast and efficient mechanism for dynamic network reconfiguration which is based on regressive deadlock recoveries instead of avoiding deadlocks. The mechanism which is referred to as DBR guarantees a deadlock-free reconfiguration based on wormhole switching (WS) and it does not require additional resources. In this approach, the need for a reliable message transmission has led to a modified WS mechanism which includes additional flits or control signals. DBR allows cycles to be formed and in such conditions when a deadlock occurs, the messages suffer from time-out. Then, this method releases the buffers and channels from the current node and thus the source retransmits the message after a random time gap. Evaluating results reveal that the mechanism shows substantial performance improvements over the other methods and it works efficiently in different topologies with various routing algorithms. 

KEYWORDS

Interconnection Networks; Dynamic Reconfiguration; Deadlock Recovery; Fault-Tolerance

Original Source Link : http://aircconline.com/vlsics/V3N5/3512vlsics02.pdf

http://airccse.org/journal/vlsi/vol3.html

MODIFIED MARCH C- WITH CONCURRENCY IN TESTING FOR EMBEDDED MEMORY APPLICATIONS

MODIFIED MARCH C- WITH CONCURRENCY IN TESTING FOR EMBEDDED MEMORY APPLICATIONS

Muddapu Parvathi1, N.Vasantha2 and K.Satya Parasad3

1Department of Electronics and Communication , M.R.I.T.S, Hyderabad, India.

2Department of Information Technology, V.C.E, Hyderabad, India.

3Department of Electronics and Communication, J.N.T.U.K, Kakinada, India.

ABSTRACT

March algorithms are known for memory testing because March-based tests are all simple and possess good fault coverage hence they are the dominant test algorithms implemented in most modern memory BIST. As March algorithms are well known algorithms for testing embedded RAMS, out of which March Cis known for finding all SAF, SOF, CF. This March C- is used frequently in the industry also. The proposed march algorithm is modified march c- algorithm which uses concurrent technique. Using this modified march c- algorithm the complexity is reduced to 8n as well as the test time is reduced greatly. Because of concurrency in testing the sequences the test results were observed in less time than the traditional March tests. This technique is applied for a memory of size 256x8 and can be extended to any memory size.

KEYWORDS

Embedded RAMS, March c-, Modified March c- algorithm, concurrent technique, complexity, traditional March tests. 

Original Source Link : http://aircconline.com/vlsics/V3N5/3512vlsics04.pdf

http://airccse.org/journal/vlsi/vol3.html

QUATERNARY LOGIC AND APPLICATIONS USING MULTIPLE QUANTUM WELL BASED SWSFETS

QUATERNARY LOGIC AND APPLICATIONS USING MULTIPLE QUANTUM WELL BASED SWSFETS

P. Gogna1,2, M. Lingalugari2, J. Chandy2, E. Heller3, E-S. Hasaneen4 and F. Jain2

1Intel Massachusetts Corp, Hudson, MA, USA

2Electrical and Computer Engineering, University of Connecticut, Storrs, CT, USA 

3RSoft Design Group, Ossining, NY, 4Electrical Engineering, Minia University, Egypt

ABSTRACT

This paper presents Spatial Wavefunction-Switched Field-Effect Transistors (SWSFET) to implement efficient quaternary logic and arithmetic functions. Various quaternary logic gates and digital building blocks are presented using SWSFETs. In addition, arithmetic operation with full adder using novel logic algebra is also presented. The SWSFET based implementation of digital logic, cache and arithmetic block results in up to 75% reduction in transistor count and up to 50% reduction in data interconnect densities. Simulations of quaternary logic gates using the BSIM equivalent models for SWSFET channels are also described.

KEYWORDS

Quaternary Logic, Multi-Channel, Nanotechnology, SWSFETs

Original Source Link : http://aircconline.com/vlsics/V3N5/3512vlsics03.pdf

http://airccse.org/journal/vlsi/vol3.html

STAND-BY LEAKAGE POWER REDUCTION IN NANOSCALE STATIC CMOS VLSI MULTIPLIER CIRCUITS USING SELF ADJUSTABLE VOLTAGE LEVEL CIRCUIT

STAND-BY LEAKAGE POWER REDUCTION IN NANOSCALE STATIC CMOS VLSI MULTIPLIER CIRCUITS USING SELF ADJUSTABLE VOLTAGE LEVEL CIRCUIT

Deeprose Subedi1 and Eugene John2

1Student, Department of Electrical and Computer Engineering, University of Texas at San Antonio, San Antonio, TX USA.

2Professor, Department of Electrical and Computer Engineering, University of Texas at San Antonio, San Antonio, TX USA.

ABSTRACT

In this paper, we performed the comparative analysis of stand-by leakage (when the circuit is idle), delay and dynamic power (when the circuit switches) of the three different parallel digital multiplier circuits implemented with two adder modules and Self Adjustable Voltage level circuit (SVL). The adder modules chosen were 28 transistor-conventional CMOS adder and 10 transistor- Static Energy Recovery CMOS adder (SERF) circuits. The multiplier modules chosen were 4Bits Array, 4bits Carry Save and 4Bits Baugh Wooley multipliers. At first, the circuits were simulated with adder modules without applying the SVL circuit. And secondly, SVL circuit was incorporated in the adder modules for simulation. In all the multiplier architectures chosen, less standby leakage power was observed being consumed by the SERF adder based multipliers applied with SVL circuit. The stand-by leakage power dissipation is 1.16µwatts in Bits array multiplier with SERF Adder applied with SVL vs. 1.39µwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit. It is 1.16µwatts in Carry Save multiplier with SERF Adder applied with SVL vs. 1.4µwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit. It is 1.67µwatts in Baugh Wooley multiplier with SERF Adder applied with SVl circuit vs. 2.74µwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit.

KEYWORDS

10 Transistor SERF Adder, SVL Circuit, Stand-by Leakage Power, Dynamic Power, Delay, Low Power Design, Sub-micron Regimes.

Original Source Link : http://aircconline.com/vlsics/V3N5/3512vlsics01.pdf

http://airccse.org/journal/vlsi/vol3.html

LOGIC OPTIMIZATION USING TECHNOLOGY INDEPENDENT MUX BASED ADDERS IN FPGA

LOGIC OPTIMIZATION USING TECHNOLOGY INDEPENDENT MUX BASED ADDERS IN FPGA

R.Uma and P.Dhavachelvan

Department of Computer Engineering, School of Engineering, Pondicherry University, Pondicherry, India

ABSTRACT

Adders form an almost obligatory component of every contemporary integrated circuit. The prerequisite of the adder is that it is primarily fast and secondarily efficient in terms of power consumption and chip area. Therefore, careful optimization of the adder is of the greatest importance. This optimization can be attained in two levels; it can be circuit or logic optimization. In circuit optimization the size of transistors are manipulated, where as in logic optimization the Boolean equations are rearranged (or manipulated) to optimize speed, area and power consumption. This paper focuses the optimization of adder through technology independent mapping. The work presents 20 different logical construction of 1-bit adder cell in CMOS logic and its performance is analyzed in terms of transistor count, delay and power dissipation. These performance issues are analyzed through Tanner EDA with TSMC MOSIS 250nm technology. From this analysis the optimized equation is chosen to construct a full adder circuit in terms of multiplexer. This logic optimized multiplexer based adders are incorporated in selected existing adders like ripple carry adder, carry look-ahead adder, carry skip adder, carry select adder, carry increment adder and carry save adder and its performance is analyzed in terms of area (slices used) and maximum combinational path delay as a function of size. The target FPGA device chosen for the implementation of these adders was Xilinx ISE 12.1 Spartan3E XC3S500-5FG320. Each adder type was implemented with bit sizes of: 8, 16, 32, 64 bits. This variety of sizes will provide with more insight about the performance of each adder in terms of area and delay as a function of size.

KEYWORDS

Technology independent mapping, Adder topologies, FPGA, Multiplexer based Adders, Logical effort, Delay calculation

Original Source Link : http://aircconline.com/vlsics/V3N4/3412vlsics12.pdf

http://airccse.org/journal/vlsi/vol3.html

MAGNETIC RESONANCE BRAIN IMAGE SEGMENTATION

M.C.Jobin Christ1 and Dr.R.M.S.Parvathi2

1Adhiyamaan College of Engineering, Dr.MGR Nagar, Hosur, India

2Sengunthar College of Engineering, Tiruchengode, India

ABSTRACT

Segmentation of tissues and structures from medical images is the first step in many image analysis applications developed for medical diagnosis. With the growing research on medical image segmentation, it is essential to categorize the research outcomes and provide researchers with an overview of the existing segmentation techniques in medical images. In this paper, different image segmentation methods applied on magnetic resonance brain images are reviewed. The selection of methods includes sources from image processing journals, conferences, books, dissertations and thesis. The conceptual details of the methods are explained and mathematical details are avoided for simplicity. Both broad and detailed categorizations of reviewed segmentation techniques are provided. The state of art research is provided with emphasis on developed techniques and image properties used by them. The methods defined are not always mutually independent. Hence, their inter relationships are also stated. Finally, conclusions are drawn summarizing commonly used techniques and their complexities in application.

KEYWORDS

MRI, Segmentation, Medical Imaging

Original Source Link : http://aircconline.com/vlsics/V3N4/3412vlsics11.pdf

http://airccse.org/journal/vlsi/vol3.html

EFFECT OF EQUAL AND MISMATCHED SIGNAL TRANSITION TIME ON POWER DISSIPATION IN GLOBAL VLSI INTERCONNECTS

EFFECT OF EQUAL AND MISMATCHED SIGNAL TRANSITION TIME ON POWER DISSIPATION IN GLOBAL VLSI INTERCONNECTS

Devendra Kumar Sharma*, Brajesh Kumar Kaushik#, and R.K.Sharma$

*Department of ECE, Meerut Institute of Engineering and Technology, Meerut, INDIA 

#Department of Electronics and Computer Engineering, Indian Institute of Technology, Roorkee, INDIA

$Department of ECE, National Institute of Technology, Kurukshetra, Haryana, INDIA

ABSTRACT

High density chips have introduced problems like crosstalk noise and power dissipation. The mismatching in transition time of the inputs occurs because different lengths of interconnects lead to different parasitic values. This paper presents the analysis of the effect of equal and unequal (mismatched) transition time of inputs on power dissipation in coupled interconnects. Further, the effect of signal skew on transition time is analysed. To demonstrate the effects, a model of two distributed RLC lines coupled capacitively and inductively is taken into consideration. Each interconnect line is 4mm long and terminated by capacitive load of 30fF. The analysis is carried out for simultaneously switching lines. The results are obtained through SPICE simulations and waveforms are generated.

KEYWORDS

Equal / Unequal rise time, Power dissipation, simultaneous switching, Signal Skew

Original Source Link : http://aircconline.com/vlsics/V3N4/3412vlsics10.pdf

http://airccse.org/journal/vlsi/vol3.html

UNIVERSAL ROTATE INVERT BUS ENCODING FOR LOW POWER VLSI

UNIVERSAL ROTATE INVERT BUS ENCODING FOR LOW POWER VLSI

Shankaranarayana Bhat M1 and D. Yogitha Jahnavi2

1Associate Professor, Department of Electronics and Communication Engineering,Manipal Institute of Technology, Manipal University, Manipal, Karnataka, India

2Student, Department of Electronics and Communication Engineering, Manipal Institute of Technology, Manipal University, Manipal, Karnataka, India

ABSTRACT

Power dissipation is an important design constraint in today’s CMOS VLSI design and is addressed widely by the researchers across the globe. Switching activity is one of the factors that affect dynamic power in a chip and several publications have suggested various techniques to reduce the same. Reduction of switching activity in the busses attains significance as bus width, bus capacitance and the clock are recording continuous uptrend. In this paper, we propose a technique for bus encoding, which, reduces the number of transitions on the bus and performs better than the existing methods such as bus invert coding and shift invert coding for random data in terms of switching activity, without the need for extra overhead in computation and circuit. However, irrespective of the bus width it needs three extra bits and does not assume anything about the nature of the data on the bus.

KEYWORDS

Bus encoding, Switching activity, CMOS VLSI, Power dissipation, Low Power Design

Original Source Link : http://aircconline.com/vlsics/V3N4/3412vlsics09.pdf

http://airccse.org/journal/vlsi/vol3.html